| /Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
[all …]
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| D | viafb.rst | 21 640x480(60, 75, 85, 100, 120 Hz), 720x480(60 Hz),
22 720x576(60 Hz), 800x600(60, 75, 85, 100, 120 Hz),
23 848x480(60 Hz), 856x480(60 Hz), 1024x512(60 Hz),
24 1024x768(60, 75, 85, 100 Hz), 1152x864(75 Hz),
25 1280x768(60 Hz), 1280x960(60 Hz), 1280x1024(60, 75, 85 Hz),
26 1440x1050(60 Hz), 1600x1200(60, 75 Hz), 1280x720(60 Hz),
27 1920x1080(60 Hz), 1400x1050(60 Hz), 800x480(60 Hz)
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-iio-frequency-adf4371 | 5 Stores the PLL frequency in Hz for channel Y.
6 Reading returns the actual frequency in Hz.
8 frequency ranging from 4000000000 Hz 8000000000 Hz.
12 frequencies from 62500000 Hz to 8000000000 Hz.
17 8000000000 Hz to 16000000000 Hz.
20 16000000000 Hz to 32000000000 Hz.
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| /Documentation/devicetree/bindings/opp/ |
| D | qcom-nvmem-cpufreq.txt | 148 opp-hz = /bits/ 64 <307200000>;
154 opp-hz = /bits/ 64 <384000000>;
160 opp-hz = /bits/ 64 <422400000>;
166 opp-hz = /bits/ 64 <460800000>;
172 opp-hz = /bits/ 64 <480000000>;
178 opp-hz = /bits/ 64 <537600000>;
184 opp-hz = /bits/ 64 <556800000>;
190 opp-hz = /bits/ 64 <614400000>;
196 opp-hz = /bits/ 64 <652800000>;
202 opp-hz = /bits/ 64 <691200000>;
[all …]
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| D | opp.txt | 85 - opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer. This is a
144 in the table have this, the OPP with highest opp-hz will be used.
148 still can't have multiple nodes with the same opp-hz value in OPP table.
209 opp-hz = /bits/ 64 <1000000000>;
216 opp-hz = /bits/ 64 <1100000000>;
222 opp-hz = /bits/ 64 <1200000000>;
288 opp-hz = /bits/ 64 <1000000000>;
295 opp-hz = /bits/ 64 <1100000000>;
301 opp-hz = /bits/ 64 <1200000000>;
364 opp-hz = /bits/ 64 <1000000000>;
[all …]
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| D | sun50i-nvmem-cpufreq.txt | 93 opp-hz = /bits/ 64 <480000000>;
102 opp-hz = /bits/ 64 <720000000>;
111 opp-hz = /bits/ 64 <816000000>;
120 opp-hz = /bits/ 64 <888000000>;
129 opp-hz = /bits/ 64 <1080000000>;
138 opp-hz = /bits/ 64 <1320000000>;
147 opp-hz = /bits/ 64 <1488000000>;
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| /Documentation/leds/ |
| D | leds-mlxcpld.rst | 59 - [0,1,1,0] = Red blink 3Hz
60 - [1,1,1,0] = Green blink 3Hz
61 - [0,1,1,1] = Red blink 6Hz
62 - [1,1,1,1] = Green blink 6Hz
104 - [0,1,1,0] = Red blink 3Hz
105 - [1,1,1,0] = Green blink 3Hz
106 - [0,1,1,1] = Red blink 6Hz
107 - [1,1,1,1] = Green blink 6Hz
114 - [1,1,1,0] = Blue blink 3Hz
115 - [1,1,1,1] = Blue blink 6Hz
[all …]
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-mediatek.txt | 34 opp-hz = /bits/ 64 <598000000>;
39 opp-hz = /bits/ 64 <747500000>;
44 opp-hz = /bits/ 64 <1040000000>;
49 opp-hz = /bits/ 64 <1196000000>;
54 opp-hz = /bits/ 64 <1300000000>;
94 opp-hz = /bits/ 64 <507000000>;
99 opp-hz = /bits/ 64 <702000000>;
104 opp-hz = /bits/ 64 <1001000000>;
109 opp-hz = /bits/ 64 <1105000000>;
114 opp-hz = /bits/ 64 <1183000000>;
[all …]
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| D | ti-cpufreq.txt | 67 opp-hz = /bits/ 64 <300000000>;
74 opp-hz = /bits/ 64 <275000000>;
81 opp-hz = /bits/ 64 <300000000>;
88 opp-hz = /bits/ 64 <500000000>;
94 opp-hz = /bits/ 64 <600000000>;
100 opp-hz = /bits/ 64 <600000000>;
106 opp-hz = /bits/ 64 <720000000>;
112 opp-hz = /bits/ 64 <720000000>;
118 opp-hz = /bits/ 64 <800000000>;
124 opp-hz = /bits/ 64 <1000000000>;
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| /Documentation/hwmon/ |
| D | adt7470.rst | 78 * 11.0 Hz
79 * 14.7 Hz
80 * 22.1 Hz
81 * 29.4 Hz
82 * 35.3 Hz
83 * 44.1 Hz
84 * 58.8 Hz
85 * 88.2 Hz
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | adi,ad7192.yaml | 50 adi,rejection-60-Hz-enable:
52 This bit enables a notch at 60 Hz when the first notch of the sinc
53 filter is at 50 Hz. When REJ60 is set, a filter notch is placed at
54 60 Hz when the sinc filter first notch is at 50 Hz. This allows
55 simultaneous 50 Hz/ 60 Hz rejection.
116 adi,rejection-60-Hz-enable;
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| D | at91-sama5d2_adc.txt | 11 - atmel,min-sample-rate-hz: Minimum sampling rate, it depends on SoC.
12 - atmel,max-sample-rate-hz: Maximum sampling rate, it depends on SoC.
41 atmel,min-sample-rate-hz = <200000>;
42 atmel,max-sample-rate-hz = <20000000>;
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| /Documentation/devicetree/bindings/gpu/ |
| D | arm,mali-bifrost.yaml | 87 opp-hz = /bits/ 64 <533000000>;
91 opp-hz = /bits/ 64 <450000000>;
95 opp-hz = /bits/ 64 <400000000>;
99 opp-hz = /bits/ 64 <350000000>;
103 opp-hz = /bits/ 64 <266000000>;
107 opp-hz = /bits/ 64 <160000000>;
111 opp-hz = /bits/ 64 <100000000>;
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| D | arm,mali-midgard.yaml | 139 opp-hz = /bits/ 64 <533000000>;
143 opp-hz = /bits/ 64 <450000000>;
147 opp-hz = /bits/ 64 <400000000>;
151 opp-hz = /bits/ 64 <350000000>;
155 opp-hz = /bits/ 64 <266000000>;
159 opp-hz = /bits/ 64 <160000000>;
163 opp-hz = /bits/ 64 <100000000>;
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| /Documentation/input/devices/ |
| D | cma3000_d0x.rst | 26 axis and supports 400, 100, 40 Hz sample frequency.
112 1: 100 Hz Measurement mode
113 2: 400 Hz Measurement mode
114 3: 40 Hz Measurement mode
116 5: 100 Hz Free fall mode
117 6: 40 Hz Free fall mode
133 (X & 0x0F) * 2.5 ms (FFTMR 400 Hz)
134 (X & 0x0F) * 10 ms (FFTMR 100 Hz)
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| /Documentation/devicetree/bindings/clock/ |
| D | cirrus,lochnagar.txt | 63 - ln-pmic-32k : 32768 Hz
64 - ln-clk-12m : 12288000 Hz
65 - ln-clk-11m : 11298600 Hz
66 - ln-clk-24m : 24576000 Hz
67 - ln-clk-22m : 22579200 Hz
68 - ln-clk-8m : 8192000 Hz
69 - ln-usb-clk-24m : 24576000 Hz
70 - ln-usb-clk-12m : 12288000 Hz
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| /Documentation/devicetree/bindings/devfreq/ |
| D | exynos-bus.txt | 206 opp-hz = /bits/ 64 <50000000>;
210 opp-hz = /bits/ 64 <100000000>;
214 opp-hz = /bits/ 64 <134000000>;
218 opp-hz = /bits/ 64 <200000000>;
222 opp-hz = /bits/ 64 <400000000>;
296 opp-hz = /bits/ 64 <50000000>;
300 opp-hz = /bits/ 64 <80000000>;
304 opp-hz = /bits/ 64 <100000000>;
308 opp-hz = /bits/ 64 <134000000>;
312 opp-hz = /bits/ 64 <200000000>;
[all …]
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| /Documentation/EDID/ |
| D | edid.S | 147 /* Bit 7 720x400 @ 70 Hz
148 Bit 6 720x400 @ 88 Hz
149 Bit 5 640x480 @ 60 Hz
150 Bit 4 640x480 @ 67 Hz
151 Bit 3 640x480 @ 72 Hz
152 Bit 2 640x480 @ 75 Hz
153 Bit 1 800x600 @ 56 Hz
154 Bit 0 800x600 @ 60 Hz */
157 /* Bit 7 800x600 @ 72 Hz
158 Bit 6 800x600 @ 75 Hz
[all …]
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| D | 800x600.S | 2 800x600.S: EDID data set for standard 800x600 60 Hz monitor
34 #define VFREQ 60 /* Hz */
36 #define ESTABLISHED_TIMING1_BITS 0x01 /* Bit 0: 800x600 @ 60Hz */
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| D | 1024x768.S | 2 1024x768.S: EDID data set for standard 1024x768 60 Hz monitor
37 #define VFREQ 60 /* Hz */
39 #define ESTABLISHED_TIMING2_BITS 0x08 /* Bit 3 -> 1024x768 @60 Hz */
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| /Documentation/scheduler/ |
| D | sched-nice-design.rst | 14 units were driven by the HZ tick, so the smallest timeslice was 1/HZ.
44 HZ=1000 it caused 1 jiffy to be 1 msec, which meant 0.1% CPU usage which
51 So for HZ=1000 we changed nice +19 to 5msecs, because that felt like the
53 But the fundamental HZ-sensitive property for nice+19 still remained,
59 within the constraints of HZ and jiffies and their nasty design level
91 enough), the scheduler was decoupled from 'time slice' and HZ concepts
94 support: with the new scheduler nice +19 tasks get a HZ-independent
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-mxs.txt | 7 - clock-frequency: Desired I2C bus clock frequency in Hz.
8 Only 100000Hz and 400000Hz modes are supported.
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| /Documentation/devicetree/bindings/sound/ |
| D | cs42l56.txt | 47 0 = 1.8Hz
48 1 = 119Hz
49 2 = 236Hz
50 3 = 464Hz
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| D | da7218.txt | 40 - dlg,dmic1-clkrate-hz : DMic1 clock frequency (Hz).
46 - dlg,dmic2-clkrate-hz : DMic2 clock frequency (Hz).
91 dlg,dmic1-clkrate-hz = <3000000>;
94 dlg,dmic2-clkrate-hz = <3000000>;
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| /Documentation/devicetree/bindings/i3c/ |
| D | cdns,i3c-master.txt | 21 - i2c-scl-hz
22 - i3c-scl-hz
37 i2c-scl-hz = <100000>;
|