Searched full:identifies (Results 1 – 25 of 192) sorted by relevance
12345678
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | marvell,sei.txt | 18 - interrupts: identifies the parent IRQ that will be triggered. 22 - interrupt-controller: identifies the node as an interrupt controller 24 - msi-controller: identifies the node as an MSI controller for the CPs
|
| D | al,alpine-msix.txt | 9 - interrupt-controller: identifies the node as an interrupt controller 10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
|
| D | mediatek,cirq.txt | 17 - interrupt-controller : Identifies the node as an interrupt controller. 21 - mediatek,ext-irq-range: Identifies external irq number range in different
|
| D | marvell,odmi-controller.txt | 13 - interrupt,controller : Identifies the node as an interrupt controller. 15 - msi-controller : Identifies the node as an MSI controller.
|
| D | marvell,armada-370-xp-mpic.txt | 6 - interrupt-controller: Identifies the node as an interrupt controller. 7 - msi-controller: Identifies the node as an PCI Message Signaled
|
| D | marvell,orion-intc.txt | 8 - interrupt-controller: identifies the node as an interrupt controller 32 - interrupt-controller: identifies the node as an interrupt controller
|
| D | img,meta-intc.txt | 14 - interrupt-controller: The presence of this property identifies the node 32 - <1st-cell>: The interrupt-number that identifies the interrupt source.
|
| D | ezchip,nps400-ic.txt | 6 - interrupt-controller : Identifies the node as an interrupt controller
|
| D | lsi,zevio-intc.txt | 9 - interrupt-controller : Identifies the node as an interrupt controller
|
| D | andestech,ativic32.txt | 11 - interrupt-controller : Identifies the node as an interrupt controller
|
| D | technologic,ts4800.txt | 9 - interrupt-controller: identifies the node as an interrupt controller
|
| D | digicolor-ic.txt | 8 - interrupt-controller : Identifies the node as an interrupt controller
|
| D | open-pic.txt | 19 - interrupt-controller: The presence of this property identifies the node 42 - <1st-cell>: The interrupt-number that identifies the interrupt source.
|
| D | aspeed,ast2400-vic.txt | 12 - interrupt-controller : Identifies the node as an interrupt controller
|
| D | mscc,ocelot-icpu-intr.txt | 7 - interrupt-controller : Identifies the node as an interrupt controller
|
| D | loongson,ls1x-intc.txt | 8 - interrupt-controller : Identifies the node as an interrupt controller
|
| D | openrisc,ompic.txt | 9 - interrupt-controller : Identifies the node as an interrupt controller.
|
| D | opencores,or1k-pic.txt | 13 - interrupt-controller : Identifies the node as an interrupt controller
|
| D | jcore,aic.txt | 13 - interrupt-controller: Identifies the node as an interrupt controller
|
| D | faraday,ftintc010.txt | 11 - interrupt-controller: Identifies the node as an interrupt controller
|
| D | img,pdc-intc.txt | 16 - interrupt-controller: The presence of this property identifies the node 34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
|
| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | raideng.txt | 12 This identifies RAID Engine block. 1 in 1.0 represents 34 This identifies the job queue interface 52 This identifies job ring. Should contain either
|
| D | mpic.txt | 87 Identifies the interrupt source. The meaning 124 cell identifies the specific error 129 The interrupt-number cell identifies 135 The interrupt-number cell identifies
|
| /Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 39 Identifies that the hart uses the RISC-V instruction set 40 and identifies the type of the hart. 50 Identifies the MMU address translation mode used on this 62 Identifies the specific RISC-V instruction set architecture
|
| /Documentation/devicetree/bindings/hwmon/ |
| D | ibmpowernv.txt | 10 - sensor-id: an opaque id provided by the firmware to the kernel, identifies a
|
12345678