Searched full:l2 (Results 1 – 25 of 91) sorted by relevance
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
15 "fsl,b4420-l2-cache-controller"
16 "fsl,b4860-l2-cache-controller"
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| D | cache_sram.txt | 11 - fsl,cache-sram-ctlr-handle : points to the L2 controller
17 fsl,cache-sram-ctlr-handle = <&L2>;
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | brcm,stb-avs-cpu-freq.txt | 6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
13 has been processed. See [2] for more information on the brcm,l2-intc node.
19 [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
37 Node brcm,avs-cpu-l2-intr
41 - compatible: must include: brcm,avs-cpu-l2-intr and
42 should include: one of brcm,bcm7271-avs-cpu-l2-intr or
43 brcm,bcm7268-avs-cpu-l2-intr
55 compatible = "brcm,l2-intc";
72 avs-cpu-l2-intr@f04d1100 {
73 compatible = "brcm,bcm7271-avs-cpu-l2-intr",
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| D | cpufreq-qcom-hw.txt | 60 L2_0: l2-cache {
76 L2_100: l2-cache {
89 L2_200: l2-cache {
102 L2_300: l2-cache {
115 L2_400: l2-cache {
128 L2_500: l2-cache {
141 L2_600: l2-cache {
154 L2_700: l2-cache {
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| D | cpufreq-dt.txt | 32 next-level-cache = <&L2>;
46 next-level-cache = <&L2>;
52 next-level-cache = <&L2>;
58 next-level-cache = <&L2>;
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| /Documentation/devicetree/bindings/arm/socionext/ |
| D | cache-uniphier.txt | 17 be 2 for L2 cache, 3 for L3 cache, etc.
23 The L2 cache must exist to use the L3 cache; the cache hierarchy must be
26 Example 1 (system with L2):
27 l2: l2-cache@500c0000 {
38 Example 2 (system with L2 and L3):
39 l2: l2-cache@500c0000 {
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| /Documentation/networking/ |
| D | ipvlan.txt | 10 the master device share the L2 with it's slave devices. I have developed this
27 MODE: l3 (default) | l3s | l2
34 (b) This command will create IPvlan link in L2 bridge mode.
35 bash# ip link add link eth0 name ipvl0 type ipvlan mode l2 bridge
36 (c) This command will create an IPvlan device in L2 private mode.
37 bash# ip link add link eth0 name ipvlan type ipvlan mode l2 private
38 (d) This command will create an IPvlan device in L2 vepa mode.
39 bash# ip link add link eth0 name ipvlan type ipvlan mode l2 vepa
43 IPvlan has two modes of operation - L2 and L3. For a given master device,
50 4.1 L2 mode:
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | brcm,l2-intc.txt | 5 - compatible: should be "brcm,l2-intc" for latched interrupt controllers
6 should be "brcm,bcm7271-l2-intc" for level interrupt controllers
16 - brcm,irq-can-wake: If present, this means the L2 controller can be used as a
22 compatible = "brcm,l2-intc";
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| D | brcm,bcm3380-l2-intc.txt | 15 - compatible: should be "brcm,bcm3380-l2-intc"
26 - brcm,irq-can-wake: if present, this means the L2 controller can be used as a
32 compatible = "brcm,bcm3380-l2-intc";
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| /Documentation/devicetree/bindings/arm/mrvl/ |
| D | feroceon.txt | 8 - reg : Address of the L2 cache control register. Mandatory for
13 l2: l2-cache@20128 {
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| D | tauros2.txt | 14 L2: l2-cache {
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| /Documentation/devicetree/bindings/arm/calxeda/ |
| D | l2ecc.txt | 1 Calxeda Highbank L2 cache ECC
4 - compatible : Should be "calxeda,hb-sregs-l2-ecc"
12 compatible = "calxeda,hb-sregs-l2-ecc";
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| /Documentation/devicetree/bindings/arm/ |
| D | l2c2x0.yaml | 7 title: ARM L2 Cache Controller
15 implementations of the L2 cache controller have compatible programming
21 Note 1: The description in this document doesn't apply to integrated L2
23 integrated L2 controllers are assumed to be all preconfigured by
39 # offset needs to be added to the address before passing down to the L2
44 # maintenance operations on L1 are broadcasted to the L2 and L2
125 description: If present then L2 is forced to Write through mode
172 description: enable parity checking on the L2 cache (L220 or PL310).
176 description: disable parity checking on the L2 cache (L220 or PL310).
180 description: enable ECC protection on the L2 cache
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| /Documentation/driver-api/ |
| D | edac.rst | 145 - CPU caches (L1 and L2)
155 For example, a cache could be composed of L1, L2 and L3 levels of cache.
156 Each CPU core would have its own L1 cache, while sharing L2 and maybe L3
164 cpu/cpu0/.. <L1 and L2 block directory>
167 /L2-cache/ce_count
169 cpu/cpu1/.. <L1 and L2 block directory>
172 /L2-cache/ce_count
176 the L1 and L2 directories would be "edac_device_block's"
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| /Documentation/devicetree/bindings/riscv/ |
| D | sifive-l2-cache.txt | 1 SiFive L2 Cache Controller
26 - reg: Physical base address and size of L2 cache controller registers map
32 - memory-region: reference to the reserved-memory for the L2 Loosely Integrated
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| /Documentation/devicetree/bindings/nds32/ |
| D | atl2c.txt | 1 * Andestech L2 cache Controller
10 representation of an Andestech L2 cache controller.
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| /Documentation/admin-guide/perf/ |
| D | qcom_l2_pmu.rst | 5 This driver supports the L2 cache clusters found in Qualcomm Technologies
6 Centriq SoCs. There are multiple physical L2 cache clusters, each with their
9 There is one logical L2 PMU exposed, which aggregates the results from
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| /Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 10 2 = nbclk (L2 Cache clock)
17 2 = l2clk (L2 Cache clock)
23 2 = l2clk (L2 Cache clock)
43 2 = l2clk (L2 Cache clock derived from CPU0 clock)
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| D | qcom,hfpll.txt | 38 such as "l2".
42 1) An HFPLL for the L2 cache.
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| /Documentation/locking/ |
| D | rt-mutex-design.rst | 139 Mutexes: L1, L2, L3, L4
143 B owns L2
144 C blocked on L2
152 E->L4->D->L3->C->L2->B->L1->A
166 E->L4->D->L3->C->L2-+
178 blocked on mutex L2::
180 G->L2->B->L1->A
186 +->L2-+
230 L1, L2, and L3, and four separate functions func1, func2, func3 and func4.
231 The following shows a locking order of L1->L2->L3, but may not actually
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| /Documentation/x86/ |
| D | resctrl_ui.rst | 38 Enable code/data prioritization in L2 cache allocations.
43 L2 and L3 CDP are controlled separately.
67 Cache resource(L3/L2) subdirectory contains the following files
329 On current generation systems there is one L3 cache per socket and L2
332 caches on a socket, multiple cores could share an L2 cache. So instead
377 This can occur when aggregate L2 external bandwidth is more than L3
379 where L2 external is 10GBps (hence aggregate L2 external bandwidth is
384 more bandwidth. This is because although the L2 external bandwidth still
424 L2 schemata file details
426 CDP is supported at L2 using the 'cdpl2' mount option. The schemata
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| /Documentation/devicetree/bindings/arm/cpu-enable-method/ |
| D | nuvoton,npcm750-smp | 30 next-level-cache = <&L2>;
39 next-level-cache = <&L2>;
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| D | marvell,berlin-smp | 28 next-level-cache = <&l2>;
35 next-level-cache = <&l2>;
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| /Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,nsp-cpu-method.txt | 27 next-level-cache = <&L2>;
34 next-level-cache = <&L2>;
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| /Documentation/devicetree/bindings/net/ |
| D | fsl-tsec-phy.txt | 69 buffer descriptors in the L2.
71 in the L2.
73 buffer to stash in the L2.
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