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/Documentation/devicetree/bindings/mfd/
Daspeed-lpc.txt2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
7 primary use case of the Aspeed LPC controller is as a slave on the bus
11 The LPC controller is represented as a multi-function device to account for the
14 "basically compatible with the [LPC registers from the] popular BMC controller
22 * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
23 physical properties of some LPC pins, configuration of serial IRQs, and
24 APB-to-LPC bridging amonst other functions.
26 * An LPC Host Interface Controller: Manages functions exposed to the host such
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
[all …]
Dcros-ec.txt6 The EC can be connect through various means (I2C, SPI, LPC, RPMSG) and the
36 Required properties (LPC):
37 - compatible: "google,cros-ec-lpc"
76 Example for LPC is not supplied as it is not yet implemented.
/Documentation/devicetree/bindings/rtc/
Drtc-st-lpc.txt1 STMicroelectronics Low Power Controller (LPC) - RTC
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Must be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
23 lpc@fde05000 {
24 compatible = "st,stih407-lpc";
[all …]
/Documentation/devicetree/bindings/timer/
Dst,stih407-lpc1 STMicroelectronics Low Power Controller (LPC) - Clocksource
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
8 [See: ../rtc/rtc-st-lpc.txt for RTC options]
12 - compatible : Must be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
23 lpc@fde05000 {
24 compatible = "st,stih407-lpc";
[all …]
/Documentation/devicetree/bindings/watchdog/
Dst_lpc_wdt.txt1 STMicroelectronics Low Power Controller (LPC) - Watchdog
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
7 [See: ../rtc/rtc-st-lpc.txt for RTC options]
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Should be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
33 lpc@fde05000 {
[all …]
/Documentation/devicetree/bindings/arm/hisilicon/
Dhisilicon-low-pin-count.txt2 Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
6 LPC device node.
10 (a) "hisilicon,hip06-lpc"
11 (b) "hisilicon,hip07-lpc"
14 - reg: base memory range where the LPC register set is mapped.
23 compatible = "hisilicon,hip06-lpc";
/Documentation/devicetree/bindings/net/
Dlpc-eth.txt4 - compatible: Should be "nxp,lpc-eth"
16 compatible = "nxp,lpc-eth";
/Documentation/ABI/stable/
Dsysfs-driver-aspeed-vuart5 will appear on the host <-> BMC LPC bus.
13 the UART will appear on the host <-> BMC LPC bus.
/Documentation/devicetree/bindings/pinctrl/
Daspeed,ast2500-pinctrl.yaml104 lpc: lpc@1e789000 {
105 compatible = "aspeed,ast2500-lpc", "simple-mfd";
112 lpc_host: lpc-host@80 {
113 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
Daspeed,ast2600-pinctrl.yaml42 LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2,
69 I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD,
Dnuvoton,npcm7xx-pinctrl.txt153 spi3quad, spi3cs2, spi3cs3, spi0cs1, lpc, lpcclk, espi, lkgpo0, lkgpo1,
/Documentation/devicetree/bindings/ipmi/
Daspeed-kcs-bmc.txt12 - kcs_chan : The LPC channel number in the controller
Dnpcm7xx-kcs-bmc.txt16 compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
/Documentation/devicetree/bindings/security/tpm/
Dtpm_tis_mmio.txt5 this interface will be implemented over Intel's LPC bus.
/Documentation/
DDMA-ISA-LPC.txt2 DMA with ISA and LPC devices
8 controller. Even though ISA is more or less dead today the LPC bus
/Documentation/devicetree/bindings/clock/
Dlpc1850-ccu.txt36 specific LPC part. Check the user manual for your specific part.
Dlpc1850-cgu.txt42 specific LPC part. Base clocks are numbered from 0 to 27.
/Documentation/i2c/busses/
Di2c-sis630.rst52 LPC Controller (rev 36)
/Documentation/devicetree/bindings/iio/frequency/
Dadf4350.txt74 lo_pll0_rx_adf4351: adf4351-rx-lpc@4 {
/Documentation/hwmon/
Dit87.rst183 All the chips supported by this driver are LPC Super-I/O chips, accessed
184 through the LPC bus (ISA-like I/O ports). The IT8712F additionally has an
Ddme1737.rst52 Include non-standard LPC addresses 0x162e and 0x164e
/Documentation/devicetree/bindings/clock/st/
Dst,flexgen.txt109 "clk-dss-lpc",