Home
last modified time | relevance | path

Searched full:mhz (Results 1 – 25 of 196) sorted by relevance

12345678

/Documentation/media/uapi/dvb/
Dfe-bandwidth-t.rst37 - .. _BANDWIDTH-1-712-MHZ:
41 - 1.712 MHz
45 - .. _BANDWIDTH-5-MHZ:
49 - 5 MHz
53 - .. _BANDWIDTH-6-MHZ:
57 - 6 MHz
61 - .. _BANDWIDTH-7-MHZ:
65 - 7 MHz
69 - .. _BANDWIDTH-8-MHZ:
73 - 8 MHz
[all …]
/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
Dstmpe.txt28 0 -> 1.625 MHz 2 || 3 -> 6.5 MHz
29 1 -> 3.25 MHz
/Documentation/devicetree/bindings/arm/
Dcpu-capacity.txt38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
128 capacity-dmips-mhz = <1024>;
139 capacity-dmips-mhz = <1024>;
[all …]
/Documentation/devicetree/bindings/clock/
Dmaxim,max9485.txt5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
15 - clocks: Input clock, must provice 27.000 MHz
34 xo-27mhz: xo-27mhz {
45 clocks = <&xo-27mhz>;
Darmada3700-periph-clock.txt36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
/Documentation/devicetree/bindings/spi/
Dspi-slave-mt27xx.txt16 - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
18 - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.
19 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
20 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
Dspi-mt65xx.txt26 - <&clk26m>: specify parent clock 26MHZ.
27 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
29 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
30 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
31 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
/Documentation/scsi/
Ddc395x.txt43 0 = 20 Mhz
44 1 = 12.2 Mhz
45 2 = 10 Mhz
46 3 = 8 Mhz
47 4 = 6.7 Mhz
49 6 = 5 Mhz
50 7 = 4 Mhz
/Documentation/devicetree/bindings/net/
Dmicrel.txt22 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
23 bit selects 25 MHz mode
25 Setting the RMII Reference Clock Select bit enables 25 MHz rather
26 than 50 MHz clock mode.
/Documentation/devicetree/bindings/display/bridge/
Dtoshiba,tc358767.txt8 clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
Dti,sn65dsi86.txt29 clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
/Documentation/devicetree/bindings/usb/
Dqcom,dwc3.txt14 "core" Master/Core clock, have to be >= 125 MHz for SS
15 operation and >= 60MHz for HS operation
17 host mode. Its frequency should be 19.2MHz.
30 19.2Mhz (192000000) for MOCK_UTMI_CLK
31 >=125Mhz (125000000) for MASTER_CLK in SS mode
32 >=60Mhz (60000000) for MASTER_CLK in HS mode
Drockchip,dwc3.txt8 "ref_clk" Controller reference clk, have to be 24 MHz
9 "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
10 "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS
11 operation and >= 30MHz for HS operation
Ddwc3-xilinx.txt7 "bus_clk" Master/Core clock, have to be >= 125 MHz for SS
8 operation and >= 60MHz for HS operation
/Documentation/arm/sunxi/
Dclocks.rst8 Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the
11 A: The 24MHz oscillator allows gating to save power. Indeed, if gated
18 24MHz 32kHz
29 24Mhz 32kHz
/Documentation/devicetree/bindings/regulator/
Dmax8952.txt15 - 0: 26 MHz
16 - 1: 13 MHz
17 - 2: 19.2 MHz
18 Defaults to 26 MHz if not specified.
/Documentation/devicetree/bindings/mips/cavium/
Ductl.txt29 /* 12MHz, 24MHz and 48MHz allowed */
/Documentation/media/v4l-drivers/
Dmax2175.rst53 samples/sec with a 10.24 MHz sck.
56 samples/sec with a 32.768 MHz sck.
61 samples/sec with a 14.88375 MHz sck.
64 samples/sec with a 7.441875 MHz sck.
/Documentation/cpu-freq/
Dcpufreq-nforce2.txt13 min_fsb defaults to FSB at boot time - 50 MHz.
17 booting with 200 MHz, 150 should always work.
/Documentation/devicetree/bindings/rtc/
Dbrcm,brcmstb-waketimer.txt3 The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
10 - clocks : The phandle to the UPG fixed clock (27Mhz domain)
/Documentation/devicetree/bindings/media/spi/
Dsony-cxd2880.txt6 - spi-max-frequency: Maximum bus speed, should be set to <55000000> (55MHz).
17 spi-max-frequency = <55000000>; /* 55MHz */
/Documentation/devicetree/bindings/ufs/
Dufshcd-pltfrm.txt41 specification allows host to provide one of the 4 frequencies (19.2 MHz,
42 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is
44 Defaults to 26 MHz(as per specification) if not specified by host.
/Documentation/devicetree/bindings/input/touchscreen/
Dstmpe.txt53 0 -> 1.625 MHz
54 1 -> 3.25 MHz
55 2 || 3 -> 6.5 MHz
79 /* 3.25 MHz ADC clock speed */

12345678