| /Documentation/devicetree/bindings/spi/ |
| D | spi-gpio.yaml | 27 miso-gpios:
28 description: GPIO spec for the MISO line to use
48 gpio-miso: false
64 miso-gpios = <&gpio 98 0>;
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| D | spi-samsung.txt | 62 miso line (to account for any lag in the miso line). The following are the
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| D | spi-controller.yaml | 117 Bus width to the SPI bus used for MISO.
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,kirkwood-pinctrl.txt | 27 mpp3 3 gpo, nand(io5), spi(miso)
37 mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
65 mpp3 3 gpo, nand(io5), spi(miso)
75 mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
109 mpp3 3 gpo, nand(io5), spi(miso)
119 mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
140 mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
158 mpp3 3 gpo, nand(io5), spi(miso)
168 mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
189 mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
[all …]
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| D | marvell,armada-370-pinctrl.txt | 35 mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
47 mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso)
57 mpp36 36 gpo, dev(a1), spi0(miso)
73 mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
95 mpp64 64 gpio, spi0(miso), spi0(cs1)
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| D | marvell,dove-pinctrl.txt | 24 mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
44 mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
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| D | marvell,armada-375-pinctrl.txt | 20 mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
49 mpp33 33 gpio, ge1(txd3), spi1(miso)
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| D | marvell,armada-39x-pinctrl.txt | 34 mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda)
43 mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
80 mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd)
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| D | marvell,armada-38x-pinctrl.txt | 34 mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), …
42 mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
76 mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(…
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| D | marvell,armada-xp-pinctrl.txt | 38 mpp17 17 gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17)
58 mpp37 37 gpio, spi0(miso)
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| D | marvell,armada-98dx3236-pinctrl.txt | 15 mpp1 1 gpio, spi0(miso), dev(ad9)
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| /Documentation/devicetree/bindings/arm/marvell/ |
| D | cp110-system-controller.txt | 101 mpp10 10 gpio, dev(readyn), ge0(txctl), spi0(miso), spi1(miso), uart0(cts), sata1(present_act)
104 mpp13 13 gpio, dev(burstn), nf(rbn0), spi1(miso), ge0(rxctl), mss_spi(miso)
105 mpp14 14 gpio, dev(bootcsn), dev(csn0), spi1(csn0), spi0(csn3), au(i2sextclk), spi0(miso), sata0(pr…
118 mpp27 27 gpio, dev(csn0), spi1(miso), mss_gpio4, ge0(rxd3), spi0(csn4), ge(mdio), sata0(present_act…
123 mpp32 32 gpio, mii(col), mii(txerr), mss_spi(miso), tdm(drx), au(i2sextclk), au(i2sdi), ge(mdio), s…
133 mpp42 42 gpio, sdio(v18_en), sdio(wr_protect), synce2(clk), au(i2smclk), mss_uart(txd), spi0(miso),…
140 mpp49 49 gpio, ge1(txclkout), mii(crs), spi1(miso), uart1(rxd), ge(mdio), pcie0(clkreq), sdio(v18_e…
149 mpp58 58 gpio, mss_i2c(sck), ptp(clk), tdm(rstn), au(i2sdi), spi0(miso), uart1(cts), led(clk), sdio…
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| D | ap806-system-controller.txt | 52 mpp1 1 gpio, sdio(cmd), spi0(miso)
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| /Documentation/driver-api/ |
| D | spi.rst | 8 line, and a "Master In, Slave Out" (MISO) data line. SPI is a full
10 another is shifted in on the MISO line. Those bits are assembled into
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| /Documentation/spi/ |
| D | butterfly.rst | 38 MISO J403.PB3/MISO pin 11/S7,nBUSY
69 MISO J403.PE6/DO pin 12/S5,nPAPEROUT
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| D | spi-summary.rst | 16 Slave Out" (MISO) signals. (Other names are also used.) There are four
57 Some chips eliminate a signal line by combining MOSI and MISO, and
184 physical SPI bus segment, with SCLK, MOSI, and MISO.
519 SPI bus (shared SCK, MOSI, MISO). Valid bus numbers start at zero. On
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | renesas,gyroadc.txt | 50 to the GyroADC, while MISO line of each TI/ADI ADC
59 to the GyroADC, while MISO line of each Maxim ADC
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-spi-byte.txt | 7 - no return value is necessary (no MISO signal)
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| /Documentation/hwmon/ |
| D | lm70.rst | 42 comprise the MOSI/MISO loop. At the end of the transfer, the 11-bit 2's
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| /Documentation/driver-api/gpio/ |
| D | drivers-on-gpio.rst | 54 of wires, at least SCK and optionally MISO, MOSI and chip select lines) using
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