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/Documentation/PCI/
Dmsi-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
5 The MSI Driver Guide HOWTO
16 the advantages of using MSI over traditional interrupt mechanisms, how
17 to change your driver to use MSI or MSI-X and some basic diagnostics to
27 The MSI capability was first specified in PCI 2.2 and was later enhanced
28 in PCI 3.0 to allow each interrupt to be masked individually. The MSI-X
30 per device than MSI and allows interrupts to be independently configured.
32 Devices may support both MSI and MSI-X, but only one can be enabled at
40 traditional pin-based interrupts.
42 Pin-based PCI interrupts are often shared amongst several devices.
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Dpci.rst1 .. SPDX-License-Identifier: GPL-2.0
7 :Authors: - Martin Mares <mj@ucw.cz>
8 - Grant Grundler <grundler@parisc-linux.org>
11 Since each CPU architecture implements different chip-sets and PCI devices
18 by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
26 "Linux PCI" <linux-pci@atrey.karlin.mff.cuni.cz> mailing list.
38 supporting hot-pluggable PCI, CardBus, and Express-Card in a single driver].
45 - Enable the device
46 - Request MMIO/IOP resources
47 - Set the DMA mask size (for both coherent and streaming DMA)
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Dpciebus-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
22 A PCI Express Port is a logical PCI-PCI Bridge structure. There
45 Express Port is a PCI-PCI Bridge device with multiple distinct
48 service drivers will compete for a single PCI-PCI Bridge device.
50 driver is loaded first, it claims a PCI-PCI Bridge Root Port. The
53 drivers load and run on a PCI-PCI Bridge device simultaneously
62 - Allow multiple service drivers to run simultaneously on
63 a PCI-PCI Bridge Port device.
65 - Allow service drivers implemented in an independent
68 - Allow one service driver to run on multiple PCI-PCI Bridge
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/Documentation/devicetree/bindings/pci/
Dxgene-pci-msi.txt1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
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Dpci-thunder-ecam.txt1 * ThunderX PCI host controller for pass-1.x silicon
3 Firmware-initialized PCI host controller to on-chip devices found on
4 some Cavium ThunderX processors. These devices have ECAM-based config
10 host-generic-pci.txt except as listed below.
13 host-generic-pci.txt:
15 - compatible : Must be "cavium,pci-host-thunder-ecam"
20 compatible = "cavium,pci-host-thunder-ecam";
22 msi-parent = <&its>;
23 msi-map = <0 &its 0x30000 0x10000>;
24 bus-range = <0 31>;
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Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
14 where <X> is the instance number of the pcie from the HW spec.
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/Documentation/misc-devices/
Dpci-endpoint-test.txt12 *) raise MSI IRQ
13 *) raise MSI-X IRQ
18 This misc driver creates /dev/pci-endpoint-test.<num> for every
23 -----
27 PCITEST_MSI: Tests message signalled interrupts. The MSI number
29 PCITEST_MSIX: Tests message signalled interrupts. The MSI-X number
32 should be passed as argument (0: Legacy, 1:MSI, 2:MSI-X).
41 [1] -> Documentation/PCI/endpoint/function/binding/pci-test.txt
/Documentation/networking/device_drivers/neterion/
Ds2io.txt1 Release notes for Neterion's (Formerly S2io) Xframe I/II PCI-X 10GbE driver.
5 - 1. Introduction
6 - 2. Identifying the adapter/interface
7 - 3. Features supported
8 - 4. Command line parameters
9 - 5. Performance suggestions
10 - 6. Available Downloads
14 This Linux driver supports Neterion's Xframe I PCI-X 1.0 and
15 Xframe II PCI-X 2.0 adapters. It supports several features
16 such as jumbo frames, MSI/MSI-X, checksum offloads, TSO, UFO and so on.
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Dvxge.txt5 --------
13 ----------------
17 firmware -
22 The functions share a 10GbE link and the pci-e bus, but hardly anything else
30 ----------------------
36 iii) PCI-SIG's I/O Virtualization
37 - Single Root mode: v1.0 (up to 17 functions)
38 - Multi-Root mode: v1.0 (up to 17 functions)
49 vi) MSI-X: (Enabled by default)
60 Comprehensive MAC-level and software statistics displayed using
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/Documentation/PCI/endpoint/
Dpci-test-function.rst1 .. SPDX-License-Identifier: GPL-2.0
11 However with the addition of EP-core in linux kernel, it is possible
45 Bit 1 raise MSI IRQ
46 Bit 2 raise MSI-X IRQ
82 This register contains the interrupt type (Legacy/MSI) triggered
83 for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
89 MSI 1
90 MSI-X 2
101 MSI [1 .. 32]
102 MSI-X [1 .. 2048]
Dpci-test-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
9 This document is a guide to help users use pci-epf-test function driver
17 ---------------------------
31 -------------------------
35 # ls /sys/bus/pci-epf/drivers
44 Creating pci-epf-test Device
45 ----------------------------
48 pci-epf-test device, the following commands can be used::
50 # mount -t configfs none /sys/kernel/config
54 The "mkdir func1" above creates the pci-epf-test function device that will
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Dpci-endpoint.rst1 .. SPDX-License-Identifier: GPL-2.0
15 vendor ID, device ID), support other services like hot-plug, power management,
22 validation, co-processor accelerator, etc.
32 ------------------------------------
53 * raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
107 Legacy Interrupt, MSI or MSI-X Interrupt.
124 the EPF device with EPC device. pci-ep-cfs.c can be used as reference for
158 ----------------------------------
212 pci-ep-cfs.c can be used as reference for using these APIs.
/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
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Dmarvell,armada-370-xp-mpic.txt1 Marvell Armada 370, 375, 38x, XP Interrupt Controller
2 -----------------------------------------------------
5 - compatible: Should be "marvell,mpic"
6 - interrupt-controller: Identifies the node as an interrupt controller.
7 - msi-controller: Identifies the node as an PCI Message Signaled
9 - #interrupt-cells: The number of cells to define the interrupts. Should be 1.
12 - reg: Should contain PMIC registers location and length. First pair
13 for the main interrupt registers, second pair for the per-CPU
21 - interrupts: If defined, then it indicates that this MPIC is
23 typically the case on Armada 375 and Armada 38x, where the MPIC is
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/Documentation/PCI/endpoint/function/binding/
Dpci-test.txt15 interrupt_pin : Should be 1 - INTA, 2 - INTB, 3 - INTC, 4 -INTD
16 msi_interrupts : Should be 1 to 32 depending on the number of MSI interrupts
18 msix_interrupts : Should be 1 to 2048 depending on the number of MSI-X
/Documentation/networking/device_drivers/intel/
Digb.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Support
46 -------
47 :Valid Range: 0-7
49 This parameter adds support for SR-IOV. It causes the driver to spawn up to
76 NOTE: When either SR-IOV mode or VMDq mode is enabled, hardware VLAN filtering
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Digbvf.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
12 - Identifying Your Adapter
13 - Additional Configurations
14 - Support
16 This driver supports Intel 82576-based virtual function devices-based virtual
17 function devices that can only be activated on kernels that support SR-IOV.
19 SR-IOV requires the correct platform and OS support.
21 The guest OS loading this driver must support MSI-X interrupts.
45 -------
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Dixgbevf.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Known Issues
15 - Support
17 This driver supports 82599, X540, X550, and X552-based virtual function devices
18 that can only be activated on kernels that support SR-IOV.
44 SR-IOV requires the correct platform and OS support.
46 The guest OS loading this driver must support MSI-X interrupts.
67 to e1000-devel@lists.sf.net.
De1000e.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2008-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Support
48 ---------------------
49 :Valid Range: 0,1,3,4,100-100000
82 - 0: Off
86 - 1: Dynamic mode
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/Documentation/networking/device_drivers/amazon/
Dena.txt13 The driver supports a range of ENA devices, is link-speed independent
17 Some ENA devices support SR-IOV. This driver is used for both the
18 SR-IOV Physical Function (PF) and Virtual Function (VF) devices.
22 is advertised by the device via the Admin Queue), a dedicated MSI-X
28 Receive-side scaling (RSS) is supported for multi-core scaling.
35 Some of the ENA devices support a working mode called Low-latency
40 1d0f:0ec2 - ENA PF
41 1d0f:1ec2 - ENA PF with LLQ support
42 1d0f:ec20 - ENA VF
43 1d0f:ec21 - ENA VF with LLQ support
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/Documentation/usb/
Ddwc3.rst11 - Convert interrupt handler to per-ep-thread-irq
13 As it turns out some DWC3-commands ~1ms to complete. Currently we spin
18 - dwc core implements a demultiplexing irq chip for interrupts per
20 to the device. If MSI provides per-endpoint interrupt this dummy
22 - interrupts are requested / allocated on usb_ep_enable() and removed on
25 - dwc3_send_gadget_ep_cmd() will sleep in wait_for_completion_timeout()
27 - the interrupt handler is split into the following pieces:
29 - primary handler of the device
34 - threaded handler of the device
37 - primary handler of the EP-interrupt
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/Documentation/ABI/stable/
Dsysfs-driver-ib_srp1 What: /sys/class/infiniband_srp/srp-<hca>-<port_number>/add_target
4 Contact: linux-rdma@vger.kernel.org
7 a comma-separated list of login parameters to this sysfs
9 * id_ext, a 16-digit hexadecimal number specifying the eight
10 byte identifier extension in the 16-byte SRP target port
13 * ioc_guid, a 16-digit hexadecimal number specifying the eight
14 byte I/O controller GUID portion of the 16-byte target port
16 * dgid, a 32-digit hexadecimal number specifying the
18 * pkey, a four-digit hexadecimal number specifying the
20 * service_id, a 16-digit hexadecimal number specifying the
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/Documentation/ABI/testing/
Dsysfs-bus-pci3 Contact: linux-pci@vger.kernel.org
12 (Note: kernels before 2.6.28 may require echo -n).
16 Contact: linux-pci@vger.kernel.org
25 (Note: kernels before 2.6.28 may require echo -n).
29 Contact: linux-pci@vger.kernel.org
46 Contact: Chris Wright <chrisw@sous-sol.org>
62 Contact: Linux PCI developers <linux-pci@vger.kernel.org>
64 Writing a non-zero value to this attribute will
66 re-discover previously removed devices.
70 Contact: Linux PCI developers <linux-pci@vger.kernel.org>
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/Documentation/scsi/
DChangeLog.megaraid_sas1 Release Date : Thu. Jun 19, 2014 17:00:00 PST 2014 -
2 (emaild-id:megaraidlinux@lsi.com)
7 Current Version : 06.803.02.00-rc1
8 Old Version : 06.803.01.00-rc1
14 -------------------------------------------------------------------------------
15 Release Date : Mon. Mar 10, 2014 17:00:00 PST 2014 -
16 (emaild-id:megaraidlinux@lsi.com)
20 Current Version : 06.803.01.00-rc1
21 Old Version : 06.700.06.00-rc1
25 4. Add Dell PowerEdge VRTX SR-IOV VF device support.
[all …]
/Documentation/driver-api/
Dmen-chameleon-bus.rst30 ----------------------
37 -----------------------------------------
43 - Multi-resource MCB devices like the VME Controller or M-Module carrier.
44 - MCB devices that need another MCB device, like SRAM for a DMA Controller's
46 - A per-carrier IRQ domain for carrier devices that have one (or more) IRQs
47 per MCB device like PCIe based carriers with MSI or MSI-X support.
54 - The MEN Chameleon Bus itself,
55 - drivers for MCB Carrier Devices and
56 - the parser for the Chameleon table.
59 -----------------
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