Searched full:msi (Results 1 – 25 of 101) sorted by relevance
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| /Documentation/devicetree/bindings/pci/ |
| D | pci-msi.txt | 2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
38 * msi-controller is a single phandle to an MSI controller
40 * msi-base is an msi-specifier describing the msi-specifier produced for the
47 the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
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| D | brcm,iproc-pcie.txt | 44 MSI support (optional):
46 For older platforms without MSI integrated in the GIC, iProc PCIe core provides
47 an event queue based MSI support. The iProc MSI uses host memories to store
48 MSI posted writes in the event queues
50 On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used
52 - msi-map: Maps a Requester ID to an MSI controller and associated MSI
55 - msi-parent: Link to the device node of the MSI controller, used when no MSI
56 sideband data is passed between the iProc PCIe controller and the MSI
60 the use of 'msi-map' and 'msi-parent':
61 Documentation/devicetree/bindings/pci/pci-msi.txt
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| D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
16 Each PCIe node needs to have property msi-parent that points to an MSI
23 + MSI node:
24 msi@79000000 {
25 compatible = "apm,xgene1-msi";
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| D | altera-pcie-msi.txt | 1 * Altera PCIe MSI controller
4 - compatible: should contain "altr,msi-1.0"
14 - msi-controller: indicates that this is MSI controller node
18 msi0: msi@0xFF200000 {
19 compatible = "altr,msi-1.0";
25 msi-controller;
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| D | aardvark-pci.txt | 16 - msi-controller: indicates that the PCIe controller can itself
17 handle MSI interrupts
18 - msi-parent: pointer to the MSI controller to be used
42 msi-controller;
43 msi-parent = <&pcie0>;
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| D | tango-pcie.txt | 11 - msi-controller
13 - interrupts: spec for misc interrupts, spec for MSI
24 msi-controller;
28 <55 IRQ_TYPE_LEVEL_HIGH>; /* MSI */
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| D | xilinx-nwl-pcie.txt | 18 "msi1, msi0": interrupt asserted when an MSI is received
27 - msi-controller: indicates that this is MSI controller node
28 - msi-parent: MSI parent of the root complex itself
45 msi-controller;
56 msi-parent = <&nwl_pcie>;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | msi.txt | 1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
17 they can address. An MSI controller may feature a number of doorbells.
22 MSI controllers may have restrictions on permitted payloads.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
35 address by some master. An MSI controller may feature a number of doorbells.
40 - msi-controller: Identifies the node as an MSI controller.
45 - #msi-cells: The number of cells in an msi-specifier, required if not zero.
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| D | fsl,ls-scfg-msi.txt | 1 * Freescale Layerscape SCFG PCIe MSI controller
5 - compatible: should be "fsl,<soc-name>-msi" to identify
6 Layerscape PCIe MSI controller block such as:
7 "fsl,ls1021a-msi"
8 "fsl,ls1043a-msi"
9 "fsl,ls1046a-msi"
10 "fsl,ls1043a-v1.1-msi"
11 "fsl,ls1012a-msi"
12 - msi-controller: indicates that this is a PCIe MSI controller node
20 Each PCIe node needs to have property msi-parent that points to
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| D | al,alpine-msix.txt | 3 See arm,gic-v3.txt for SPI and MSI definitions.
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
22 msi-controller;
23 al,msi-base-spi = <160>;
24 al,msi-num-spis = <160>;
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| D | arm,gic-v3.yaml | 107 msi-controller:
152 mbi-ranges: [ msi-controller ]
153 msi-controller: [ mbi-ranges ]
163 # msi-controller is preferred, but allow other names
164 "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
168 used to route Message Signalled Interrupts (MSI) to the CPUs.
173 msi-controller: true
175 "#msi-cells":
177 The single msi-cell is the DeviceID of the device which will generate
178 the MSI.
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| D | arm,gic.yaml | 136 * GICv2m extension for MSI/MSI-x support (Optional)
138 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
145 msi-controller: true
149 description: GICv2m MSI interface register base and size
151 arm,msi-base-spi:
153 this property should contain the SPI base of the MSI frame, overriding
157 arm,msi-num-spis:
165 - msi-controller
198 // GICv2m extension for MSI/MSI-x support
214 msi-controller;
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| D | marvell,odmi-controller.txt | 2 * Marvell ODMI for MSI support
5 which can be used by on-board peripheral for MSI interrupts.
15 - msi-controller : Identifies the node as an MSI controller.
35 msi-controller;
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| D | hisilicon,mbigen-v2.txt | 6 MBI is kind of msi interrupt only used on Non-PCI devices.
28 - msi-parent: Specifies the MSI controller this mbigen use.
29 For more detail information,please refer to the generic msi-parent binding in
30 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
56 msi-parent = <&its_dsa 0x40b1c>;
63 msi-parent = <&its_dsa 0x40b0e>;
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | msi-pic.txt | 1 * Freescale MSI interrupt controller
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
17 region must be added because different MSI group has different MSIIR1 offset.
21 be set as edge sensitive. If msi-available-ranges is present, only
25 - msi-available-ranges: use <start count> style section to define which
26 msi interrupt can be used in the 256 msi interrupts. This property is
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| /Documentation/PCI/ |
| D | msi-howto.rst | 5 The MSI Driver Guide HOWTO
16 the advantages of using MSI over traditional interrupt mechanisms, how
17 to change your driver to use MSI or MSI-X and some basic diagnostics to
27 The MSI capability was first specified in PCI 2.2 and was later enhanced
28 in PCI 3.0 to allow each interrupt to be masked individually. The MSI-X
30 per device than MSI and allows interrupts to be independently configured.
32 Devices may support both MSI and MSI-X, but only one can be enabled at
73 driver has to set up the device to use MSI or MSI-X. Not all machines
80 To support MSI or MSI-X, the kernel must be built with the CONFIG_PCI_MSI
86 Using MSI
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| /Documentation/PCI/endpoint/ |
| D | pci-test-howto.rst | 79 to change the vendorid and the number of MSI interrupts used by the function
158 SET IRQ TYPE TO MSI: OKAY
191 SET IRQ TYPE TO MSI-X: OKAY
192 MSI-X1: OKAY
193 MSI-X2: OKAY
194 MSI-X3: OKAY
195 MSI-X4: OKAY
196 MSI-X5: OKAY
197 MSI-X6: OKAY
198 MSI-X7: OKAY
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| D | pci-test-function.rst | 45 Bit 1 raise MSI IRQ
46 Bit 2 raise MSI-X IRQ
82 This register contains the interrupt type (Legacy/MSI) triggered
83 for the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands.
89 MSI 1
90 MSI-X 2
101 MSI [1 .. 32]
102 MSI-X [1 .. 2048]
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| /Documentation/devicetree/bindings/mailbox/ |
| D | brcm,iproc-flexrm-mbox.txt | 14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
16 interrupts) to CPU. There is one MSI for each FlexRM ring.
17 Refer devicetree/bindings/interrupt-controller/msi.txt
23 The 2nd cell contains MSI completion threshold. This is the
25 one MSI interrupt to CPU.
27 The 3nd cell contains MSI timer value representing time for
31 specified by this cell then it will inject one MSI interrupt
46 msi-parent = <&gic_its 0x7f00>;
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| /Documentation/devicetree/bindings/powerpc/4xx/ |
| D | hsta.txt | 10 Currently only the MSI support is used by Linux using the following
14 - compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
15 - reg : register mapping for the HSTA MSI space
16 - interrupts : ordered interrupt mapping for each MSI in the register
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| /Documentation/misc-devices/ |
| D | spear-pcie-gadget.txt | 35 no_of_msi :zero if MSI is not enabled by host. A positive value is the
36 number of MSI vector granted.
48 INTA, MSI or NO_INT). Select MSI only when you have programmed
50 no_of_msi :number of MSI vector needed.
52 send_msi :write MSI vector to be sent.
110 if MSI is to be used as interrupt, program no of msi vector needed (say4)
113 select MSI as interrupt type
114 # echo MSI >> int_type
124 wait till msi is enabled
126 Should return 4 (number of requested MSI vector)
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| D | pci-endpoint-test.txt | 12 *) raise MSI IRQ
13 *) raise MSI-X IRQ
27 PCITEST_MSI: Tests message signalled interrupts. The MSI number
29 PCITEST_MSIX: Tests message signalled interrupts. The MSI-X number
32 should be passed as argument (0: Legacy, 1:MSI, 2:MSI-X).
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| /Documentation/ABI/testing/ |
| D | sysfs-platform-msi-laptop | 1 What: /sys/devices/platform/msi-laptop-pf/lcd_level
8 What: /sys/devices/platform/msi-laptop-pf/auto_brightness
17 What: /sys/devices/platform/msi-laptop-pf/wlan
24 What: /sys/devices/platform/msi-laptop-pf/bluetooth
33 What: /sys/devices/platform/msi-laptop-pf/touchpad
41 What: /sys/devices/platform/msi-laptop-pf/turbo_mode
54 What: /sys/devices/platform/msi-laptop-pf/eco_mode
64 What: /sys/devices/platform/msi-laptop-pf/turbo_cooldown
75 What: /sys/devices/platform/msi-laptop-pf/auto_fan
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| /Documentation/devicetree/bindings/dma/ |
| D | mv-xor-v2.txt | 10 - msi-parent: Phandle to the MSI-capable interrupt controller used for
26 msi-parent = <&gic_v2m0>;
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| /Documentation/devicetree/bindings/iommu/ |
| D | arm,smmu-v3.txt | 51 - msi-parent : See the generic MSI binding described in
52 devicetree/bindings/interrupt-controller/msi.txt
53 for a description of the msi-parent property.
76 msi-parent = <&its 0xff0000>;
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