Searched full:nano (Results 1 – 18 of 18) sorted by relevance
68 enable (WE signal) in nano seconds.71 enable (OE signal) in nano seconds.74 access in nano seconds.77 access in nano seconds.80 accesses in nano seconds.82 - mpmc,turn-round-delay: Delay between access to memory banks in nano
7 title: NXP i.MX8M Nano Clock Control Module Binding13 NXP i.MX8M Nano clock control module is an integrated clock controller, which46 for the full list of i.MX8M Nano clock IDs.
16 the pad setting value like pull-up on this pin. Please refer to i.MX8M Nano
5 Author: Christer Weinigel <wingel@nano-system.com>
48 Platform specific PWM period value. unit is nano.
38 Defines the interval between two poll cycles in nano seconds.
139 char *hash_alg_name = "sha1-padlock-nano";
46 an SoC into an FPGA. The below is an example of programming a De0 Nano
318 9 means 12.5 nano-seconds synchronous period319 10 means 25 nano-seconds synchronous period320 11 means 30 nano-seconds synchronous period321 12 means 50 nano-seconds synchronous period565 Since SCSI devices shall release the BUS at most 800 nano-seconds after SCSI
457 10 means 25 nano-seconds synchronous period458 11 means 30 nano-seconds synchronous period459 12 means 50 nano-seconds synchronous period998 Since SCSI devices shall release the BUS at most 800 nano-seconds after SCSI 1365 Periods are in nano-seconds and speeds are in Mega-transfers per second.
254 - DViCO FusionHDTV 5 PCI nano
362 - PCTV QuatroStick nano (520e)
371 linaro@linaro-nano:~$ ./perf list pmu377 linaro@linaro-nano:~$398 root@linaro-nano:~# perf record -e cs_etm/@tmc_etr0/u --per-thread program
93 sudo nano fb_defio
377 - description: Linksprite PCDuino3 Nano379 - const: linksprite,pcduino3-nano
223 reach timeout of n * 640 nano seconds.
9 Copyright 2002 Christer Weingel <wingel@nano-system.com>
575 based on 5% of SRTT, capped by this sysctl, in nano seconds.