Searched full:pio (Results 1 – 25 of 76) sorted by relevance
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| /Documentation/w1/slaves/ |
| D | w1_ds28e04.rst | 7 * Maxim DS28E04-100 4096-Bit Addressable 1-Wire EEPROM with PIO
20 Support is provided through the sysfs files "eeprom" and "pio". CRC checking
35 PIO Access
37 The 2 PIOs of the DS28E04-100 are accessible via the "pio" sysfs file.
39 The current status of the PIO's is returned as an 8 bit value. Bit 0/1
40 represent the state of PIO_0/PIO_1. Bits 2..7 do not care. The PIO's are
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| D | w1_ds2406.rst | 21 current state of each switch, with PIO A in bit 0 and PIO B in bit 1. The
23 work with. output is writable; bits 0 and 1 control PIO A and B,
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| D | w1_ds2413.rst | 20 The DS2413 chip has two open-drain outputs (PIO A and PIO B).
40 You can set the PIO pins using the "output" file.
56 When writing output, the master must repeat the PIO Output Data byte in
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| /Documentation/mips/ |
| D | au1xxx_ide.rst | 58 - timing parameters for PIO mode 0/1/2/3/4
67 - enable the PIO+DBDMA mode
75 The AU1XXX IDE driver supported all PIO modes - PIO mode 0/1/2/3/4 - and all
78 To change the PIO mode use the program hdparm with option -p, e.g.
79 'hdparm -p0 [device]' for PIO mode 0. To enable the MWDMA mode use the option
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | anx7814.txt | 30 hpd-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
31 pd-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
32 reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>;
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-st.txt | 4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
9 Pull Up (PU) are driven by the related PIO block.
11 ST pinctrl driver controls PIO multiplexing block and also interacts with
33 - compatible : should be "st,stih407-<pio-block>-pinctrl"
114 Every PIO is represented with 4-7 parameters depending on retime configuration.
117 -bank : Should be bank phandle to which this PIO belongs.
118 -offset : Offset in the PIO bank.
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| D | allwinner,sunxi-pinctrl.txt | 110 pio: pinctrl@1c20800 {
152 interrupt-parent = <&pio>;
163 gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | ektf2127.txt | 19 interrupt-parent = <&pio>;
21 power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>;
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| D | silead_gsl1680.txt | 35 interrupt-parent = <&pio>;
37 power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>;
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| D | chipone_icn8318.txt | 32 interrupt-parent = <&pio>;
36 wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
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| D | zet6223.txt | 26 interrupt-parent = <&pio>;
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| /Documentation/ABI/stable/ |
| D | sysfs-driver-w1_ds28e04 | 1 What: /sys/bus/w1/devices/.../pio
4 Description: read/write the contents of the two PIO's of the DS28E04-100
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| /Documentation/devicetree/bindings/ata/ |
| D | pata-arasan.txt | 23 - arasan,broken-pio: if present, PIO mode is unusable
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| /Documentation/spi/ |
| D | pxa2xx.rst | 10 - SSP PIO and SSP DMA data transfers.
106 fifo overruns (especially in PIO mode transfers). Good default values are::
211 DMA and PIO I/O Support
213 The pxa2xx_spi driver supports both DMA and interrupt driven PIO message
214 transfers. The driver defaults to PIO mode and DMA transfers must be enabled
222 always use PIO transfers
226 use PIO transfers
235 use PIO transfer
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| /Documentation/networking/ |
| D | z8530book.rst | 27 The PIO synchronous mode supports the most common Z8530 wiring. Here the
29 machine but not to the DMA subsystem. When running PIO the Z8530 has
43 gives better performance than pure PIO mode but is nowhere near as ideal
157 PIO mode the interface is programmed up to use interrupt driven PIO.
160 latencies caused by other drivers, notably IDE in PIO mode. Because the
173 To active PIO mode sending and receiving the ``z8530_sync_open`` is called.
177 The :c:func:`z8530_sync_close()` function shuts down a PIO
224 machines. The PIO mode makes no real assumptions.
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-altera.txt | 5 - "altr,pio-1.0"
34 compatible = "altr,pio-1.0";
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| /Documentation/devicetree/bindings/sound/ |
| D | mt2701-cs42448.txt | 41 i2s1-in-sel-gpio1 = <&pio 53 0>;
42 i2s1-in-sel-gpio2 = <&pio 54 0>;
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-orion.txt | 14 additionally to the normal indirect access (PIO) mode. The values
63 and its chip-selects that are used in the direct mode instead of PIO
66 are used in the default indirect (PIO) mode):
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| D | spi-mt65xx.txt | 62 cs-gpios = <&pio 105 GPIO_ACTIVE_LOW>, <&pio 72 GPIO_ACTIVE_LOW>;
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | pincfg.txt | 4 - pio-map : array of pin configurations. Each pin is defined by 6
30 pio-map = <
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| D | ucc.txt | 14 - pio-handle : The phandle for the Parallel I/O port configuration.
67 pio-handle = <140001>;
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| /Documentation/devicetree/bindings/phy/ |
| D | sun4i-usb-phy.txt | 63 usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */
64 usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
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| /Documentation/devicetree/bindings/display/panel/ |
| D | feiyang,fy07024di26a30d.txt | 18 reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */
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| /Documentation/devicetree/bindings/usb/ |
| D | usb-conn-gpio.txt | 27 id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
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| /Documentation/i2c/ |
| D | dma-considerations.rst | 9 DMA for it will likely add more overhead than a plain PIO transfer.
51 buffer could not be allocated. Fall back to PIO in that case.
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