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/Documentation/devicetree/bindings/arm/
Dl2c2x0.yaml14 PL220/PL310 and variants) based level 2 cache controller. All these various
33 - arm,pl310-cache
36 # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
37 - bcm,bcm11351-a2-pl310-cache
41 - brcm,bcm11351-a2-pl310-cache
51 # with arm,pl310-cache controller.
110 I/O coherent mode. Valid only when the arm,pl310-cache compatible
163 description: The default behavior of the L220 or PL310 cache
172 description: enable parity checking on the L2 cache (L220 or PL310).
176 description: disable parity checking on the L2 cache (L220 or PL310).
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/Documentation/devicetree/bindings/interrupt-controller/
Dst,sti-irq-syscfg.txt5 and PL310 L2 Cache IRQs are controlled using System Configuration registers.
/Documentation/arm/
Dmarvel.rst400 - Core: ARM Cortex-A9, PL310 L2CC
409 - Core: Quad Core ARM Cortex-A9, PL310 L2CC