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/Documentation/devicetree/bindings/c6x/
Dclocks.txt1 C6X PLL Clock Controllers
10 - compatible: "ti,c64x+pll"
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
33 compatible = "ti,c6472-pll", "ti,c64x+pll";
[all …]
/Documentation/devicetree/bindings/clock/
Dqca,ath79-pll.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
6 - compatible: has to be "qca,<soctype>-pll" and one of the following
8 - "qca,ar7100-pll"
9 - "qca,ar7240-pll"
10 - "qca,ar9130-pll"
11 - "qca,ar9330-pll"
12 - "qca,ar9340-pll"
13 - "qca,qca9550-pll"
24 pll-controller@18050000 {
25 compatible = "qca,ar9132-pll", "qca,ar9130-pll";
Dkeystone-pll.txt3 Binding for keystone PLLs. The main PLL IP typically has a multiplier,
4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
6 PLL is controlled by a PLL controller registers along with memory mapped
15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
17 - reg - pll control0 and pll multipler registers
19 post-divider registers are applicable only for main pll clock
26 compatible = "ti,keystone,main-pll-clock";
35 compatible = "ti,keystone,pll-clock";
37 clock-output-names = "pa-pll-clk";
44 - compatible : shall be "ti,keystone,pll-mux-clock"
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Dvt8500.txt9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
15 Required properties for PLL clocks:
16 - reg : shall be the control register offset from PMC base for the pll clock.
23 be a pll output.
61 compatible = "wm,wm8650-pll-clock";
Dsnps,hsdk-pll-clock.txt1 Binding for the HSDK Generic PLL clock
8 - compatible: should be "snps,hsdk-<name>-pll-clock"
9 "snps,hsdk-core-pll-clock"
10 "snps,hsdk-gp-pll-clock"
11 "snps,hsdk-hdmi-pll-clock"
13 - clocks: shall be the input parent clock phandle for the PLL.
24 compatible = "snps,hsdk-core-pll-clock";
Dsnps,pll-clock.txt1 Binding for the AXS10X Generic PLL clock
8 - compatible: should be "snps,axs10x-<name>-pll-clock"
9 "snps,axs10x-arc-pll-clock"
10 "snps,axs10x-pgu-pll-clock"
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
24 compatible = "snps,axs10x-arc-pll-clock";
Dqoriq-clock.txt5 multiple phase locked loops (PLL) to create a variety of frequencies
69 platform PLL.
87 4 platform pll n=pll/(n+1). For example, when n=1,
116 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
117 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
124 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
125 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
128 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
129 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
131 * 0 - equal to the PLL frequency
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Dti-keystone-pllctrl.txt1 * Device tree bindings for Texas Instruments keystone pll controller
3 The main pll controller used to drive theC66x CorePacs, the switch fabric,
5 the NETCP modules) requires a PLL Controller to manage the various clock
12 - reg: contains offset/length value for pll controller
17 pllctrl: pll-controller@02310000 {
Dclock-bindings.txt104 pll: pll@4c000 {
105 compatible = "vendor,some-pll-interface"
110 clock-output-names = "pll", "pll-switched";
114 * and the high frequency switched PLL output for register
120 clocks = <&osc 0>, <&pll 1>;
125 low-frequency reference clock, a PLL device to generate a higher frequency
129 * The PLL is both a clock provider and a clock consumer. It uses the clock
131 ("pll" and "pll-switched").
133 register clock connected to the PLL clock (the "pll-switched" signal)
153 clocks = <&osc 0>, <&pll 1>;
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Daxs10x-i2s-pll-clock.txt1 Binding for the AXS10X I2S PLL clock
8 - compatible: shall be "snps,axs10x-i2s-pll-clock"
9 - reg : address and length of the I2S PLL register set.
10 - clocks: shall be the input parent clock phandle for the PLL.
21 compatible = "snps,axs10x-i2s-pll-clock";
Dsilabs,si5351.txt30 - silabs,pll-source: pair of (number, source) for each pll. Allows
31 to overwrite clock source of pll A (number=0) or B (number=1).
49 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
51 - silabs,pll-master: boolean, multisynth can change pll frequency.
52 - silabs,pll-reset: boolean, clock output can reset its pll.
83 silabs,pll-source = <0 0>, <1 0>;
98 silabs,pll-master;
114 pll-master;
Dbrcm,iproc-clocks.txt8 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
11 Required properties for a PLL and its leaf clocks:
14 Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
18 Have a value of <1> since there are more than 1 leaf clock of a given PLL
22 clock control registers required for the PLL
25 The input parent clock phandle for the PLL. For most iProc PLLs, this is an
89 PLL and leaf clock compatible strings for Cygnus are:
97 The following table defines the set of PLL/clock index and ID for Cygnus.
142 PLL and leaf clock compatible strings for Hurricane 2 are:
145 The following table defines the set of PLL/clock for Hurricane 2:
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Dxgene.txt9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
16 Required properties for SoC or PCP PLL clocks:
17 - reg : shall be the physical PLL register address for the pll clock.
21 - clock-output-names : shall be the name of the PLL referenced by derive
23 Optional properties for PLL clocks:
24 - clock-names : shall be the name of the PLL. If missing, use the device name.
32 Optional properties for PLL clocks:
Ddove-divider-clock.txt1 PLL divider based Dove clocks
3 Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
18 - reg : shall be the register address of the Core PLL and Clock Divider
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
Dmoxa,moxart-clock.txt7 MOXA ART SoCs allow to determine PLL output and APB frequencies
11 PLL:
14 - compatible : Must be "moxa,moxart-pll-clock"
38 compatible = "moxa,moxart-pll-clock";
Drenesas,h8s2678-pll-clock.txt1 Renesas H8S2678 PLL clock
7 - compatible: Must be "renesas,h8s2678-pll-clock"
19 compatible = "renesas,h8s2678-pll-clock";
/Documentation/devicetree/bindings/sound/
Dpcm512x.txt20 is absent the device will be configured to clock from BCLK. If pll-in
21 and pll-out are specified in addition to a clock, the device is
24 - pll-in, pll-out : gpio pins used to connect the pll using <1>
26 given pll-in pin and PLL output on the given pll-out pin. An
27 external connection from the pll-out pin to the SCLK pin is assumed.
50 pll-in = <3>;
51 pll-out = <6>;
Dtas2552.txt19 internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM
20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
22 defined values to select and configure the PLL and PDM reference clocks.
/Documentation/media/dvb-drivers/
Dcards.rst27 tuner/PLL chips, and not all combinations are supported. Often
28 the demodulator and tuner/PLL chip are inside a metal box for
38 - cx24110 : Conexant HM1221/HM1811 (cx24110 or cx24106 demod, cx24108 PLL)
39 - grundig_29504-491 : Grundig 29504-491 (Philips TDA8083 demodulator), tsa5522 PLL
41 - stv0299 : Alps BSRU6 (tsa5059 PLL), LG TDQB-S00x (tsa5059 PLL),
42 LG TDQF-S001F (sl1935 PLL), Philips SU1278 (tua6100 PLL),
43 Philips SU1278SH (tsa5059 PLL), Samsung TBMU24112IMB, Technisat Sky2Pc with bios Rev. 2.6
46 - ves1820 : various (ves1820 demodulator, sp5659c or spXXXX PLL)
47 - at76c651 : Atmel AT76c651(B) with DAT7021 PLL
50 - alps_tdlb7 : Alps TDLB7 (sp8870 demodulator, sp5659 PLL)
[all …]
/Documentation/devicetree/bindings/usb/
Dnvidia,tegra124-xusb.txt49 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
50 - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
51 - avdd-usb-ss-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
53 - hvdd-usb-ss-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
59 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
60 - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
61 - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
62 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
127 avdd-pll-utmip-supply = <&vddio_1v8>;
128 avdd-pll-erefe-supply = <&avdd_1v05_run>;
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/Documentation/devicetree/bindings/display/ti/
Dti,dra7-dss.txt20 Some DRA7xx SoCs have one dedicated video PLL, some have two. These properties
25 - clocks: handle to video1 pll clock and video2 pll clock
60 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
62 - reg-names: "wp", "pll", "phy", "core"
66 - clocks: handles to fclk and pll clock
Dti,omap5-dss.txt64 - reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
65 - reg-names: "proto", "phy", "pll"
69 - clocks: handles to fclk and pll clock
86 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
88 - reg-names: "wp", "pll", "phy", "core"
92 - clocks: handles to fclk and pll clock
/Documentation/devicetree/bindings/ufs/
Dufs-qcom.txt20 - vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply
29 - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply
42 vdda-pll-supply = <&pma8084_l12>;
44 vdda-pll-max-microamp = <1000>;
/Documentation/devicetree/bindings/media/i2c/
Dadv7343.txt14 micro ampere level. All DACs and the internal PLL
16 - adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows
17 internal PLL 1 circuit to be powered down and the
39 adi,power-mode-pll-ctrl;
/Documentation/devicetree/bindings/clock/ti/davinci/
Dpll.txt1 Binding for TI DaVinci PLL Controllers
3 The PLL provides clocks to most of the components on the SoC. In addition
4 to the PLL itself, this controller also contains bypasses, gates, dividers,
26 Describes the main PLL clock output (before POSTDIV). The node name must
41 Describes the AUXCLK output of the PLL. The node name must be "auxclk".
48 Describes the OBSCLK output of the PLL. The node name must be "obsclk".

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