Searched full:peripheral (Results 1 – 25 of 281) sorted by relevance
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| /Documentation/driver-api/memory-devices/ |
| D | ti-gpmc.rst | 24 functioning of the peripheral, while peripheral has another set of
25 timings. To have peripheral work with gpmc, peripheral timings has to
27 translated depends on the connected peripheral. Also there is a
32 from gpmc peripheral timings. struct gpmc_device_timings fields has to
33 be updated with timings from the datasheet of the peripheral that is
34 connected to gpmc. A few of the peripheral timings can be fed either
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
40 field as required by peripheral, educate generic timing routine to
42 Then there may be cases where peripheral datasheet doesn't mention
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| /Documentation/ABI/testing/ |
| D | sysfs-platform-renesas_usb3 | 10 "host" - switching mode from peripheral to host.
11 "peripheral" - switching mode from host to peripheral.
15 "peripheral" - The mode is peripheral now.
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| D | sysfs-platform-phy-rcar-gen3-usb2 | 10 "host" - switching mode from peripheral to host.
11 "peripheral" - switching mode from host to peripheral.
15 "peripheral" - The mode is peripheral now.
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| /Documentation/devicetree/bindings/phy/ |
| D | meson-gxl-usb3-phy.txt | 10 - and peripheral mode/OTG detection
11 - clock-names: must contain "phy" and "peripheral"
14 - peripheral mode/OTG detection
15 - reset-names: must contain "phy" and "peripheral"
28 clock-names = "phy", "peripheral";
30 reset-names = "phy", "peripheral";
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| D | hix5hd2-phy.txt | 11 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
12 - hisilicon,power-reg: offset and bit number within peripheral-syscon,
20 hisilicon,peripheral-syscon = <&peripheral_ctrl>;
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| D | phy-hi3798cv200-combphy.txt | 6 registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and
21 peripheral controller, as a 3 integers tuple:
27 - The device node should be a child of peripheral controller that contains
29 Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller
34 perictrl: peripheral-controller@8a20000 {
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| D | phy-hi6220-usb.txt | 7 - hisilicon,peripheral-syscon: phandle of syscon used to control phy.
15 hisilicon,peripheral-syscon = <&sys_ctrl>;
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| /Documentation/devicetree/bindings/clock/ |
| D | pistachio-clock.txt | 4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
44 Peripheral clock controller:
47 The peripheral clock controller generates clocks for the DDR, ROM, and other
48 peripherals. The peripheral system clock ("periph_sys") generated by the core
49 clock controller is the input clock to the peripheral clock controller.
53 - reg: Must contain the base address and length of the peripheral clock
58 - clock-names: Must include "periph_sys", the peripheral system clock generated
71 Peripheral general control:
74 The peripheral general control block generates system interface clocks and
75 resets for various peripherals. It also contains miscellaneous peripheral
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| D | mvebu-gated-clock.txt | 4 peripheral clocks to be gated to save some power. The clock consumer
11 ID Clock Peripheral
28 ID Clock Peripheral
55 ID Clock Peripheral
82 ID Clock Peripheral
96 ID Clock Peripheral
123 ID Clock Peripheral
133 ID Clock Peripheral
149 22 pdma Peripheral DMA
156 ID Clock Peripheral
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| D | armada3700-periph-clock.txt | 1 * Peripheral Clock bindings for Marvell Armada 37xx SoCs
3 Marvell Armada 37xx SoCs provide peripheral clocks which are
4 used as clock source for the peripheral of the SoC.
9 The peripheral clock consumer should specify the desired clock by
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| D | imx7ulp-clock.txt | 4 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
23 processor, system, peripheral bus and external memory interface clocks,
24 source selection for peripheral clocks and control of power saving
36 Peripheral Clock Control (PCC) modules:
38 The Peripheral Clock Control (PCC) is responsible for clock selection,
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| /Documentation/devicetree/bindings/display/ |
| D | mipi-dsi-bus.txt | 15 The following assumes that only a single peripheral is connected to a DSI
34 conjunction with another DSI host to drive the same peripheral. Hardware
39 DSI peripheral
52 - reg: The virtual channel number of a DSI peripheral. Must be in the range
58 that the peripheral responds to.
59 - If the virtual channels that a peripheral responds to are consecutive, the
79 connected to this peripheral. Each DSI host's output endpoint can be linked to
80 an input endpoint of the DSI peripheral.
87 - (1), (2) and (3) are examples of a DSI host and peripheral on the DSI bus
89 - (4) is an example of a peripheral on a I2C control bus connected to a
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| /Documentation/devicetree/bindings/iommu/ |
| D | samsung,sysmmu.txt | 4 physical memory chunks visible as a contiguous region to DMA-capable peripheral
13 System MMUs are in many to one relation with peripheral devices, i.e. single
14 peripheral device might have multiple System MMUs (usually one for each bus
15 master), but one System MMU can handle transactions from only one peripheral
16 device. The relation between a System MMU and the peripheral device needs to be
17 defined in device node of the peripheral device.
27 For information on assigning System MMU controller to its peripheral devices,
41 of peripheral device this SYSMMU belongs to).
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | img,pdc-intc.txt | 27 shared SysWake interrupt, and remaining specifies shall be PDC peripheral
35 0-7: Peripheral interrupts
39 flags as follows (only 4 valid for peripheral interrupts):
74 <30 4 /* level */>, /* Peripheral 0 (RTC) */
75 <29 4 /* level */>, /* Peripheral 1 (IR) */
76 <31 4 /* level */>; /* Peripheral 2 (WDT) */
82 * An SoC peripheral that is wired through the PDC.
88 // Interrupt source Peripheral 0
89 interrupts = <0 /* Peripheral 0 (RTC) */
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| /Documentation/devicetree/bindings/display/panel/ |
| D | sharp,lq101r1sx01.txt | 7 Each of the DSI channels controls a separate DSI peripheral. The peripheral
9 peripheral and controls the device. The 'link2' property contains a phandle
10 to the peripheral driven by the second link (DSI-LINK2, right or odd).
20 - reg: DSI virtual channel of the peripheral
23 - link2: phandle to the DSI peripheral on the secondary link. Note that the
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| /Documentation/devicetree/bindings/mfd/ |
| D | qcom,spmi-pmic.txt | 40 Required properties for peripheral child nodes:
41 - compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name.
43 Optional properties for peripheral child nodes:
50 example below the rtc device node represents a peripheral of pm8941
51 SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1.
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| /Documentation/devicetree/bindings/usb/ |
| D | atmel-usb.txt | 10 - clocks: Should reference the peripheral, host and system clocks
12 "ohci_clk" for the peripheral clock
37 - clocks: Should reference the peripheral and the UTMI clocks
39 "ehci_clk" for the peripheral clock
60 - clocks: Should reference the peripheral and the AHB clocks
62 "pclk" for the peripheral clock
87 - clocks: Should reference the peripheral and host clocks
89 "pclk" for the peripheral clock
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| D | renesas,usb3-peri.txt | 1 Renesas Electronics USB3.0 Peripheral driver
18 - reg: Base address and length of the register for the USB3.0 Peripheral
19 - interrupts: Interrupt specifier for the USB3.0 Peripheral
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| D | cdns-usb3.txt | 16 "peripheral" - interrupt used by device driver
22 - dr_mode: Should be one of "host", "peripheral" or "otg".
38 interrupt-names = "host", "peripheral", "otg";
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| /Documentation/devicetree/bindings/dma/ |
| D | atmel-xdma.txt | 15 - bit 14: DIF, destination interface identifier, used to get the peripheral
17 - bit 30-24: PERID, peripheral identifier.
37 - bit 14: DIF, destination interface identifier, used to get the peripheral
39 - bit 30-24: PERID, peripheral identifier.
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| /Documentation/devicetree/bindings/spi/ |
| D | atmel-quadspi.txt | 1 * Atmel Quad Serial Peripheral Interface (QSPI)
13 - clocks: Should reference the peripheral clock and the QSPI system
15 - clock-names: Should contain "pclk" for the peripheral clock and "qspick"
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| D | qcom,spi-geni-qcom.txt | 1 GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
4 (an output FIFO and an input FIFO) for serial peripheral interface (SPI)
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| /Documentation/driver-api/ |
| D | spi.rst | 1 Serial Peripheral Interface (SPI)
4 SPI is the "Serial Peripheral Interface", widely used with embedded
13 normally used for each peripheral, plus sometimes an interrupt.
19 peripherals and does not implement such a peripheral itself. (Interfaces
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| /Documentation/devicetree/bindings/input/ |
| D | ti,nspire-keypad.txt | 6 - reg: Physical base address of the peripheral and length of memory mapped
9 - interrupts: The interrupt number for the peripheral.
16 - clocks: The clock this peripheral is attached to.
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| /Documentation/devicetree/bindings/reset/ |
| D | nxp,lpc1850-rgu.txt | 14 See table below for valid peripheral reset numbers. Numbers not
18 Reset Peripheral
62 the reset signals and the connected block/peripheral.
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