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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-mt7622.txt | 10 - #gpio-cells: Should be two. The first cell is the pin number and the
23 phrase "pin configuration node".
25 MT7622 pin configuration nodes act as a container for an arbitrary number of
27 pin, a group, or a list of pins or groups. This configuration can include the
28 mux function to select on those pin(s)/group(s), and various pin configuration
55 - pins: An array of strings. Each string contains the name of a pin.
83 pins can be referenced via the pin names as the below table shown and the
88 Pin #: Valid values for pins
90 PIN 0: "GPIO_A"
91 PIN 1: "I2S1_IN"
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| D | pinctrl-bindings.txt | 3 Hardware modules that control pin multiplexing or configuration parameters
4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
5 controllers. Each pin controller must be represented as a node in device tree,
8 Hardware modules whose signals are affected by pin configuration are
12 For a client device to operate correctly, certain pin controllers must
13 set up certain specific pin configurations. Some client devices need a
14 single static pin configuration, e.g. set up during initialization. Others
21 for client device device tree nodes to map those state names to the pin
24 Note that pin controllers themselves may also be client devices of themselves.
25 For example, a pin controller may set up its own "active" state when the
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| D | samsung-pinctrl.txt | 1 Samsung GPIO and Pin Mux/Config controller
3 Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
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| D | renesas,pfc-pinctrl.txt | 1 * Renesas Pin Function Controller (GPIO and Pin Mux/Config)
3 The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0,
7 Pin Control
13 - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
14 - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
15 - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
16 - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
17 - "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller.
18 - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
19 - "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller.
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| D | renesas,rza1-pinctrl.txt | 1 Renesas RZ/A1 combined Pin and GPIO controller
3 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller,
5 Pin multiplexing and GPIO configuration is performed on a per-pin basis
9 Up to 8 different alternate function modes exist for each single pin.
11 Pin controller node
21 address base and length of the memory area where the pin controller
25 Pin controller node for RZ/A1H SoC (r7s72100)
27 pinctrl: pin-controller@fcfe3000 {
36 The child nodes of the pin controller node describe a pin multiplexing
39 - Pin multiplexing sub-nodes:
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| D | cnxt,cx92755-pinctrl.txt | 1 Conexant Digicolor CX92755 General Purpose Pin Mapping
3 This document describes the device tree binding of the pin mapping hardware
7 === Pin Controller Node ===
12 - reg: Base address of the General Purpose Pin Mapping register block and the
15 - #gpio-cells: Must be <2>. The first cell is the pin number and the
28 As a pin controller device, in addition to the required properties, this node
29 should also contain the pin configuration nodes that client devices reference,
34 === Pin Configuration Node ===
36 Each pin configuration node is a sub-node of the pin controller node and is a
37 container of an arbitrary number of subnodes, called pin group nodes in this
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| D | sprd,pinctrl.txt | 1 * Spreadtrum Pin Controller
3 The Spreadtrum pin controller are organized in 3 blocks (types).
9 driving level": One pin can output 3.0v or 1.8v, depending on the
11 slect 3.0v, then the pin can output 3.0v. "system control" is used
23 bits in one global control register as one pin, thus we should
24 record every pin's bit offset, bit width and register offset to
25 configure this field (pin).
28 register definition, and each register described one pin is used
29 to configure the pin sleep mode, function select and sleep related
33 PUBCP system, TGLDSP system and AGDSP system. And the pin sleep
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| D | renesas,rza2-pinctrl.txt | 1 Renesas RZ/A2 combined Pin and GPIO controller
3 The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO controller.
4 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
7 Up to 8 different alternate function modes exist for each single pin.
9 Pin controller node
16 Address base and length of the memory area where the pin controller
19 This pin controller also controls pins as GPIO
25 Example: Pin controller node for RZ/A2M SoC (r7s9210)
27 pinctrl: pin-controller@fcffe000 {
39 The child nodes of the pin controller designate pins to be used for
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| D | renesas,rzn1-pinctrl.txt | 3 Pin controller node
11 - reg: Address base and length of the memory area where the pin controller
18 pinctrl: pin-controller@40067000 {
28 The child nodes of the pin controller node describe a pin multiplexing
31 - Pin multiplexing sub-nodes:
32 A pin multiplexing sub-node describes how to configure a set of
33 (or a single) pin in some desired alternate function mode.
34 A single sub-node may define several pin configurations.
36 pin properties usage.
38 The allowed generic formats for a pin multiplexing sub-node are the
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| D | brcm,bcm11351-pinctrl.txt | 1 Broadcom BCM281xx Pin Controller
3 This is a pin controller for the Broadcom BCM281xx SoC family, which includes
6 === Pin Controller Node ===
21 As a pin controller device, in addition to the required properties, this node
22 should also contain the pin configuration nodes that client devices reference,
25 === Pin Configuration Node ===
27 Each pin configuration node is a sub-node of the pin controller node and is a
28 container of an arbitrary number of subnodes, called pin group nodes in this
33 "pin configuration node".
35 === Pin Group Node ===
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| D | pinctrl-sx150x.txt | 5 pin controller, GPIO, and interrupt bindings.
38 Required properties for pin configuration sub-nodes:
41 Optional properties for pin configuration sub-nodes:
43 - bias-disable: disable any pin bias, except the OSCIO pin
44 - bias-pull-up: pull up the pin, except the OSCIO pin
45 - bias-pull-down: pull down the pin, except the OSCIO pin
46 - bias-pull-pin-default: use pin-default pull state, except the OSCIO pin
48 …ve-open-drain: drive with open drain only for sx1507q, sx1508q and sx1509q and except the OSCIO pin
49 - output-low: set the pin to output mode with low level
50 - output-high: set the pin to output mode with high level
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| D | marvell,armada-37xx-pinctrl.txt | 1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
11 GPIO and pin controller:
18 of the phrase "pin configuration node".
45 - pin 11 (GPIO1-11)
49 - pin 12
53 - pin 13
57 - pin 14
61 - pin 7
65 - pin 6
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| D | atmel,at91-pinctrl.txt | 12 phrase "pin configuration node".
14 Atmel AT91 pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'pins' selects the function mode(also named pin
17 mode) this pin can work on and the 'config' configures various pad settings
23 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
41 For each peripheral/bank we will descibe in a u32 if a pin can be
42 configured in it by putting 1 to the pin bit (1 << pin)
82 Required properties for pin configuration node:
89 PULL_UP (1 << 0): indicate this pin needs a pull up.
90 MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive.
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| D | brcm,nsp-gpio.txt | 12 Must be two. The first cell is the GPIO pin number (within the
13 controller's pin space) and the second cell is used for the following:
30 Specifies the mapping between gpio controller and pin-controllers pins.
32 1. Phandle of pin-controller.
33 2. GPIO base pin offset.
34 3 Pin-control base pin offset.
35 4. number of gpio pins which are linearly mapped from pin base.
39 The list of pins (within the controller's own pin space) that properties
40 in the node apply to. Pin names are "gpio-<pin>"
43 Disable pin bias
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| D | nvidia,tegra194-pinmux.txt | 11 phrase "pin configuration node".
13 Tegra's pin configuration nodes act as a container for an arbitrary number of
15 pin, a group, or a list of pins or groups. This configuration can include the
16 mux function to select on those pin(s)/group(s), and various pin configuration
19 See the TRM to determine which properties and values apply to each pin/group.
24 - nvidia,pins : An array of strings. Each string contains the name of a pin or
29 pin or group.
30 - nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
34 - nvidia,enable-input: Integer. Enable the pin's input path.
40 - nvidia,lock: Integer. Lock the pin configuration against further changes
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| D | cortina,gemini-pinctrl.txt | 1 Cortina Systems Gemini pin controller
3 This pin controller is found in the Cortina Systems Gemini SoC family,
4 see further arm/gemini.txt. It is a purely group-based multiplexing pin
7 The pin controller node must be a subnode of the system controller node.
12 Subnodes of the pin controller contain pin control multiplexing set-up
13 and pin configuration of individual pins.
15 Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
16 and generic pin config nodes.
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| D | sprd,sc9860-pinctrl.txt | 1 * Spreadtrum SC9860 Pin Controller
8 - reg: The register address of pin controller device.
9 - pins : An array of strings, each string containing the name of a pin.
18 - bias-disable: Disable pin bias.
19 - bias-pull-down: Pull down on pin.
20 - bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
22 - input-enable: Enable pin input.
23 - input-disable: Enable pin output.
24 - output-high: Set the pin as an output level high.
25 - output-low: Set the pin as an output level low.
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| /Documentation/devicetree/bindings/sound/ |
| D | rt5659.txt | 23 - realtek,dmic1-data-pin
25 1: using IN2N pin as dmic1 data pin
26 2: using GPIO5 pin as dmic1 data pin
27 3: using GPIO9 pin as dmic1 data pin
28 4: using GPIO11 pin as dmic1 data pin
30 - realtek,dmic2-data-pin
32 1: using IN2P pin as dmic2 data pin
33 2: using GPIO6 pin as dmic2 data pin
34 3: using GPIO10 pin as dmic2 data pin
35 4: using GPIO12 pin as dmic2 data pin
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| D | rt5645.txt | 16 a GPIO spec for the external headphone detect pin. If jd-mode = 0,
22 - realtek,dmic1-data-pin
24 1: using IN2P pin as dmic1 data pin
25 2: using GPIO6 pin as dmic1 data pin
26 3: using GPIO10 pin as dmic1 data pin
27 4: using GPIO12 pin as dmic1 data pin
29 - realtek,dmic2-data-pin
31 1: using IN2N pin as dmic2 data pin
32 2: using GPIO5 pin as dmic2 data pin
33 3: using GPIO11 pin as dmic2 data pin
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| D | rt5682.txt | 15 - realtek,dmic1-data-pin
17 1: using GPIO2 pin as dmic1 data pin
18 2: using GPIO5 pin as dmic1 data pin
20 - realtek,dmic1-clk-pin
21 0: using GPIO1 pin as dmic1 clock pin
22 1: using GPIO3 pin as dmic1 clock pin
28 - realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
47 realtek,dmic1-data-pin = <1>;
48 realtek,dmic1-clk-pin = <1>;
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| D | rt5668.txt | 15 - realtek,dmic1-data-pin
17 1: using GPIO2 pin as dmic1 data pin
18 2: using GPIO5 pin as dmic1 data pin
20 - realtek,dmic1-clk-pin
21 0: using GPIO1 pin as dmic1 clock pin
22 1: using GPIO3 pin as dmic1 clock pin
28 - realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
47 realtek,dmic1-data-pin = <1>;
48 realtek,dmic1-clk-pin = <1>;
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| D | rt5665.txt | 21 - realtek,dmic1-data-pin
23 1: using GPIO4 pin as dmic1 data pin
24 2: using IN2N pin as dmic2 data pin
26 - realtek,dmic2-data-pin
28 1: using GPIO5 pin as dmic2 data pin
29 2: using IN2P pin as dmic2 data pin
35 - realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | pincfg.txt | 1 * Pin configuration nodes
4 - pio-map : array of pin configurations. Each pin is defined by 6
5 integers. The six numbers are respectively: port, pin, dir,
7 - port : port number of the pin; 0-6 represent port A-G in UM.
8 - pin : pin number in the port.
9 - dir : direction of the pin, should encode as follows:
11 0 = The pin is disabled
12 1 = The pin is an output
13 2 = The pin is an input
14 3 = The pin is I/O
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| /Documentation/driver-api/ |
| D | pinctl.rst | 2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
20 Definition of PIN CONTROLLER:
22 - A pin controller is a piece of hardware, usually a set of registers, that
26 Definition of PIN:
30 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
31 there may be several such number spaces in a system. This pin space may
33 pin exists.
35 When a PIN CONTROLLER is instantiated, it will register a descriptor to the
36 pin control framework, and this descriptor contains an array of pin descriptors
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| /Documentation/devicetree/bindings/net/ |
| D | icplus-ip101ag.txt | 4 - IP101GR (32-pin QFN package)
6 - IP101GA (48-pin LQFP package)
10 - IP101A (48-pin LQFP package)
11 - IP101AH (48-pin LQFP package)
13 Optional properties for the IP101GR (32-pin QFN package):
16 pin 21 ("RXER/INTR_32") will output the receive error status.
19 pin 21 ("RXER/INTR_32") will output the interrupt signal.
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