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/Documentation/livepatch/
Dcallbacks.rst42 * Post-patch
48 active), used to clean up post-patch callback
51 * Post-unpatch
61 symmetry: pre-patch callbacks have a post-unpatch counterpart and
62 post-patch callbacks have a pre-unpatch counterpart. An unpatch
90 No post-patch, pre-unpatch, or post-unpatch callbacks will be executed
96 will only occur if their corresponding post-patch callback executed).
100 only the post-unpatch callback will be called.
118 patch the data *after* patching is complete with a post-patch callback,
126 may be possible to implement similar updates via pre/post-patch
[all …]
/Documentation/devicetree/bindings/clock/
Dkeystone-pll.txt4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
29 reg-names = "control", "multiplier", "post-divider";
Dst,stm32-rcc.txt87 12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor)
88 13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor)
/Documentation/devicetree/bindings/input/
Dhid-over-i2c.txt30 - post-power-on-delay-ms
33 - post-power-on-delay-ms: time required by the device after enabling its regulators
/Documentation/devicetree/bindings/display/
Damlogic,meson-vpu.yaml20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
37 VPP: Video Post Processing
40 The Video Post Processing is in charge of the scaling and blending of the
43 scaler and a "post-blending" to merge with the OSD Planes.
/Documentation/gpu/
Dmeson.rst19 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
33 Video Post Processing
37 :doc: Video Post Processing
/Documentation/devicetree/bindings/ata/
Dsata_highbank.txt28 - calxeda,post-clocks: a u32 that indicates the number of additional clock
43 calxeda,post-clocks = <0>;
/Documentation/devicetree/bindings/net/
Dfsl-fec.txt54 - phy-reset-post-delay : Post reset delay in milliseconds. If present then
55 a delay of phy-reset-post-delay milliseconds will be observed after the
Dhisilicon-femac.txt22 The 3rd cell is reset post-delay in micro seconds.
/Documentation/ABI/testing/
Dsysfs-class-fpga-manager35 * write complete = Doing post programming steps
36 * write complete error = Error while doing post programming
/Documentation/devicetree/bindings/leds/backlight/
Dpwm-backlight.txt13 - post-pwm-on-delay-ms: Delay in ms between setting an initial (non-zero) PWM
45 post-pwm-on-delay-ms = <10>;
/Documentation/media/uapi/dvb/
Dfrontend-stat-properties.rst155 .. _DTV-STAT-POST-ERROR-BIT-COUNT:
169 :ref:`DTV_STAT_POST_TOTAL_BIT_COUNT <DTV-STAT-POST-TOTAL-BIT-COUNT>`.
184 .. _DTV-STAT-POST-TOTAL-BIT-COUNT:
191 :ref:`DTV_STAT_POST_ERROR_BIT_COUNT <DTV-STAT-POST-ERROR-BIT-COUNT>`
209 :ref:`DTV_STAT_POST_ERROR_BIT_COUNT <DTV-STAT-POST-ERROR-BIT-COUNT>`.
/Documentation/networking/
Dax25.txt10 subscribed to post but of course that means you might miss an answer.
Dbridge.rst19 If you still have questions, don't hesitate to post to the mailing list
Dtc-actions-env-rules.txt23 Post on netdev if something is unclear.
/Documentation/sound/soc/
Dmachine.rst24 /* the pre and post PM functions are used to do any PM work before and
47 The machine driver has pre and post versions of suspend and resume to take care
/Documentation/filesystems/
Defivarfs.txt19 UEFI variables causes the system firmware to fail to POST, efivarfs
/Documentation/devicetree/bindings/phy/
Dapm-xgene-phy.txt43 - apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of
/Documentation/trace/
Devents-msr.rst35 The trace data can be post processed with the postprocess/decode_msr.py script::
/Documentation/media/v4l-drivers/
Dcx18.rst23 then post to the video4linux or ivtv-users mailing list.
/Documentation/devicetree/bindings/mmc/
Dmmc-pwrseq-simple.txt19 - post-power-on-delay-ms : Delay in ms after powering the card and
/Documentation/hwmon/
Dds620.rst26 returned via sysfs displays post decimal positions.
/Documentation/accounting/
Dcgroupstats.rst15 The current model for cgroupstats is a pull, a push model (to post
/Documentation/devicetree/bindings/mailbox/
Dstm32-ipcc.txt3 The IPCC block provides a non blocking signaling mechanism to post and
/Documentation/cpu-freq/
Dindex.txt41 you can report bugs, problems or submit patches. To post a message,

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