Home
last modified time | relevance | path

Searched full:ram (Results 1 – 25 of 201) sorted by relevance

123456789

/Documentation/admin-guide/blockdev/
Dramdisk.rst2 Using the RAM disk block device with Linux
10 4) An Example of Creating a Compressed RAM Disk
16 The RAM disk driver is a way to use main system memory as a block device. It
22 The RAM disk dynamically grows as more space is required. It does this by using
23 RAM from the buffer cache. The driver marks the buffers it is using as dirty
26 The RAM disk supports up to 16 RAM disks by default, and can be reconfigured
27 to support an unlimited number of RAM disks (at your own risk). Just change
31 To use RAM disk support with your system, run './MAKEDEV ram' from the /dev
32 directory. RAM disks are all major number 1, and start with minor number 0
35 The new RAM disk also has the ability to load compressed RAM disk images,
[all …]
/Documentation/devicetree/bindings/net/
Ddavinci_emac.txt12 - ti,davinci-ctrl-ram-offset: offset to control module ram
13 - ti,davinci-ctrl-ram-size: size of control module ram
24 - ti,davinci-no-bd-ram: boolean, does EMAC have BD RAM?
35 ti,davinci-ctrl-ram-offset = <0>;
36 ti,davinci-ctrl-ram-size = <0x2000>;
/Documentation/translations/zh_CN/arm/
DBooting40 1、设置和初始化 RAM。
47 1、设置和初始化 RAM
53 引导装载程序应该找到并初始化系统中所有内核用于保持系统变量数据的 RAM。
55 RAM，或可能使用对这个设备已知的 RAM 信息，还可能使用任何引导装载程序
117 标签列表应该保存在系统的 RAM 中。
120 建议放在 RAM 的头 16KiB 中。
126 RAM 中，并用启动数据初始化它。dtb 格式在文档
132 dtb 必须置于内核自解压不会覆盖的内存区。建议将其放置于 RAM 的头 16KiB
146 zImage 也可以被放在系统 RAM（任意位置）中被调用。注意：内核使用映像
147 基地址的前 16KB RAM 空间来保存页表。建议将映像置于 RAM 的 32KB 处。
[all …]
/Documentation/devicetree/bindings/net/can/
Dm_can.txt7 registers map and Message RAM
18 - bosch,mram-cfg : Message RAM configuration data.
20 RAM and each element(e.g Rx FIFO or Tx Buffer and etc)
21 number in Message RAM is also configurable,
23 private Message RAM are used by this M_CAN controller.
28 The 'offset' is an address offset of the Message RAM
31 RAM. The remain cells are used to specify how many
43 Please refer to 2.4.1 Message RAM Configuration in
Dti_hecc.txt9 - reg: addresses and lengths of the register spaces for 'hecc', 'hecc-ram'
11 - reg-names :"hecc", "hecc-ram", "mbx"
29 reg-names = "hecc", "hecc-ram", "mbx";
/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra20-emc.txt9 - nvidia,use-ram-code : If present, the sub-nodes will be addressed
12 irrespective of ram-code configuration.
30 Embedded Memory Controller ram-code table
32 If the emc node has the nvidia,use-ram-code property present, then the
34 apply for which ram-code settings.
36 If the emc node lacks the nvidia,use-ram-code property, this level is omitted
42 - nvidia,ram-code : the binary representation of the ram-code board strappings
64 on a 2-pin "ram code" bootstrap setting on the board. The values of
/Documentation/arm/
Dporting.rst25 to be located in RAM, it can be in flash or other read-only or
30 This must be pointing at RAM. The decompressor will zero initialise
43 Physical address to place the initial RAM disk. Only relevant if
48 Virtual address of the initial RAM disk. The following constraint
62 Physical start address of the first bank of RAM.
65 Virtual start address of the first bank of RAM. During the kernel
101 last virtual RAM address (found using variable high_memory).
105 between virtual RAM and the vmalloc area. We do this to allow
113 `pram` specifies the physical start address of RAM. Must always
Dbooting.rst19 1. Setup and initialise the RAM.
27 1. Setup and initialise RAM
35 The boot loader is expected to find and initialise all RAM that the
38 to automatically locate and size all RAM, or it may use knowledge of
39 the RAM in the machine, or any other method the boot loader designer
120 The tagged list should be stored in system RAM.
124 it. The recommended placement is in the first 16KiB of RAM.
129 The boot loader must load a device tree image (dtb) into system ram
142 A safe location is just above the 128MiB boundary from start of RAM.
158 be loaded just above the 128MiB boundary from the start of RAM as
[all …]
Dtcm.rst8 This is usually just a few (4-64) KiB of RAM inside the ARM
32 place you put it, it will mask any underlying RAM from the
33 CPU so it is usually wise not to overlap any physical RAM with
55 - Idle loops where all external RAM is set to self-refresh
56 retention mode, so only on-chip RAM is accessible by
61 the external RAM controller.
72 - Have the remaining TCM RAM added to a special
138 printk("Hello TCM executed from ITCM RAM\n");
/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-etb1013 Description: (RW) Disables write access to the Trace RAM by stopping the
16 into the Trace RAM following the trigger event is equal to the
23 Description: (R) Defines the depth, in words, of the trace RAM in powers of
37 Description: (R) Shows the value held by the ETB RAM Read Pointer register
38 that is used to read entries from the Trace RAM over the APB
46 Description: (R) Shows the value held by the ETB RAM Write Pointer register
48 the CoreSight bus into the Trace RAM. The value is read directly
Dsysfs-bus-coresight-devices-tmc5 Description: (RW) Disables write access to the Trace RAM by stopping the
14 Description: (R) Defines the size, in 32-bit words, of the local RAM buffer.
28 Description: (R) Shows the value held by the TMC RAM Read Pointer register
29 that is used to read entries from the Trace RAM over the APB
37 Description: (R) Shows the value held by the TMC RAM Write Pointer register
39 the CoreSight bus into the Trace RAM. The value is read directly
/Documentation/devicetree/bindings/soc/qcom/
Dqcom,smem.txt17 - qcom,rpm-msg-ram:
30 at 0xfa00000 and the RPM message ram at 0xfc428000:
47 qcom,rpm-msg-ram = <&rpm_msg_ram>;
54 compatible = "qcom,rpm-msg-ram";
Dqcom,aoss-qmp.txt6 SoC has it's own block of message RAM and IRQ for communication with the AOSS.
7 The protocol used to communicate in the message RAM is known as Qualcomm
26 Definition: the base address and size of the message RAM for this
66 The following example represents the AOSS side-channel message RAM and the
/Documentation/vm/
Dfrontswap.rst9 swapped pages are saved in RAM (or a RAM-like device) instead of a swap disk.
21 a synchronous concurrency-safe page-oriented "pseudo-RAM device" conforming
23 in-kernel compressed memory, aka "zcache", or future RAM-like devices);
24 this pseudo-RAM device is not directly accessible or addressable by the
88 useful for write-balancing for some RAM-like devices). Swap pages (and
89 evicted page-cache pages) are a great use for this kind of slower-than-RAM-
90 but-much-faster-than-disk "pseudo-RAM device" and the frontswap (and
95 provides a huge amount of flexibility for more dynamic, flexible RAM
100 that can be safely kept in RAM. Zcache essentially trades off CPU
108 as in zcache, but then "remotified" to another system's RAM. This
[all …]
Dcleancache.rst122 saved in transcendent memory (RAM that is otherwise not directly
128 fast kernel-directly-addressable RAM and slower DMA/asynchronous devices.
132 balancing for some RAM-like devices). Evicted page-cache pages (and
133 swap pages) are a great use for this kind of slower-than-RAM-but-much-
140 virtual machines. This is really hard to do with RAM and efforts to
144 of flexibility for more dynamic, flexible RAM multiplexing.
146 "fallow" hypervisor-owned RAM to not only be "time-shared" between multiple
148 optimize RAM utilization. And when guest OS's are induced to surrender
149 underutilized RAM (e.g. with "self-ballooning"), page cache pages
156 the proposed "RAMster" driver shares RAM across multiple physical
[all …]
/Documentation/admin-guide/
Dinitrd.rst1 Using the initial RAM disk (initrd)
8 initrd provides the capability to load a RAM disk by the boot loader.
9 This RAM disk can then be mounted as the root file system and programs
27 1) the boot loader loads the kernel and the initial RAM disk
28 2) the kernel converts initrd into a "normal" RAM disk and
58 Loads the specified file as the initial RAM disk. When using LILO, you
59 have to specify the RAM disk image file in /etc/lilo.conf, using the
64 initrd data is preserved but it is not converted to a RAM disk and
77 with the RAM disk mounted as root.
117 Second, the kernel has to be compiled with RAM disk support and with
[all …]
Dramoops.rst11 Ramoops is an oops/panic logger that writes its logs to RAM before the system
13 needs a system with persistent RAM so that the content of that area can
46 to life (i.e. a watchdog triggered). In such cases, RAM may be somewhat
113 You can specify either RAM memory or peripheral devices' memory. However, when
114 specifying RAM, be sure to reserve the memory by issuing memblock_reserve()
132 a stored record from RAM, simply unlink the respective pstore file.
/Documentation/devicetree/bindings/soc/ti/
Dkeystone-navigator-qmss.txt6 processors(PDSP), linking RAM, descriptor pools and infrastructure
12 Linking RAM registers are used to link the descriptors which are stored in
13 descriptor RAM. Descriptor RAM is configurable as internal or external memory.
14 The QMSS driver manages the PDSP setups, linking RAM regions,
24 - linkram0 : <address size> for internal link ram, where size is the total
25 link ram entries.
26 - linkram1 : <address size> for external link ram, where size is the total
27 external link ram entries. If the address is specified as "0"
38 - Queue status RAM.
109 - PDSP internal RAM region.
/Documentation/filesystems/
Dtmpfs.txt14 you gain swapping and limit checking. Another similar thing is the RAM
15 disk (/dev/ram*), which simulates a fixed size hard disk in physical
16 RAM, where you have to create an ordinary filesystem on top. Ramdisks
60 default is half of your physical RAM without swap. If you
65 is half of the number of your physical RAM pages, or (on a
66 machine with highmem) the number of lowmem RAM pages,
71 to limit this tmpfs instance to that percentage of your physical RAM:
141 RAM/SWAP in 10240 inodes and it is only accessible by root.
/Documentation/arm/keystone/
Dknav-qmss.rst12 processors(PDSP), linking RAM, descriptor pools and infrastructure
18 Linking RAM registers are used to link the descriptors which are stored in
19 descriptor RAM. Descriptor RAM is configurable as internal or external memory.
20 The QMSS driver manages the PDSP setups, linking RAM regions,
/Documentation/power/
Dinterface.rst18 - 'mem' (Suspend-to-RAM)
24 for Suspend-to-RAM and Power-On Suspend depends on the capabilities of the
40 - 'suspend' (trigger a Suspend-to-RAM transition)
47 does that, for example). The 'suspend' option is available if Suspend-to-RAM
64 around 2/5 of available RAM by default.
/Documentation/devicetree/bindings/misc/
Dnvidia,tegra20-apbmisc.txt14 - nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).
/Documentation/w1/slaves/
Dw1_ds2423.rst20 read sequence of w1_slave file initiates the read of counters and ram
24 value and associated ram buffer is outpputed to own line.
34 - 1 byte from ram page
38 - 31 remaining bytes from the ram page
/Documentation/translations/zh_CN/arm64/
Dbooting.txt47 1、设置和初始化 RAM
53 1、设置和初始化 RAM
58 引导装载程序应该找到并初始化系统中所有内核用于保持系统变量数据的 RAM。
60 RAM，或可能使用对这个设备已知的 RAM 信息，还可能是引导装载程序设计者
154 x0 = 系统 RAM 中设备树数据块（dtb）的物理地址。
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dcpm.txt34 parameter RAM region (if it has one).
36 * Multi-User RAM (MURAM)
38 The multi-user/dual-ported RAM is expressed as a bus under the CPM node.

123456789