Searched full:reset (Results 1 – 25 of 956) sorted by relevance
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| /Documentation/devicetree/bindings/reset/ |
| D | zynq-reset.txt | 1 Xilinx Zynq Reset Manager
8 - compatible: "xlnx,zynq-reset"
12 - #reset-cells: Must be 1
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
24 Reset outputs:
25 0 : soft reset
26 32 : ddr reset
27 64 : topsw reset
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| D | reset.txt | 1 = Reset Signal Device Tree Bindings =
3 This binding is intended to represent the hardware reset signals present
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
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| D | uniphier-reset.txt | 1 UniPhier reset controller
4 System reset
9 "socionext,uniphier-ld4-reset" - for LD4 SoC
10 "socionext,uniphier-pro4-reset" - for Pro4 SoC
11 "socionext,uniphier-sld8-reset" - for sLD8 SoC
12 "socionext,uniphier-pro5-reset" - for Pro5 SoC
13 "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
14 "socionext,uniphier-ld11-reset" - for LD11 SoC
15 "socionext,uniphier-ld20-reset" - for LD20 SoC
16 "socionext,uniphier-pxs3-reset" - for PXs3 SoC
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| D | ti-syscon-reset.txt | 1 TI SysCon Reset Controller
4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
12 A SysCon Reset Controller node defines a device that uses a syscon node
13 and provides reset management functionality for various hardware modules
16 SysCon Reset Controller Node
18 Each of the reset provider/controller nodes should be a child of a syscon
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
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| D | snps,hsdk-reset.txt | 1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
9 - reg: should always contain 2 pairs address - length: first for reset
10 configuration register and second for corresponding SW reset and status bits
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
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| D | snps,axs10x-reset.txt | 1 Binding for the AXS10x reset controller
4 to control reset signals of selected peripherals. For example DW GMAC, etc...
6 represents up-to 32 reset lines.
11 This binding uses the common reset binding[1].
13 [1] Documentation/devicetree/bindings/reset/reset.txt
16 - compatible: should be "snps,axs10x-reset".
17 - reg: should always contain pair address - length: for creg reset
19 - #reset-cells: from common reset binding; Should always be set to 1.
22 reset: reset-controller@11220 {
23 compatible = "snps,axs10x-reset";
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| D | fsl,imx7-src.txt | 1 Freescale i.MX7 System Reset Controller
4 Please also refer to reset.txt in this directory for common reset
15 - #reset-cells: 1, see below
19 src: reset-controller@30390000 {
23 #reset-cells = <1>;
27 Specifying reset lines connected to IP modules
30 The system reset controller can be used to reset various set of
31 peripherals. Device nodes that need access to reset lines should
32 specify them as a reset phandle in their corresponding node as
33 specified in reset.txt.
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| D | img,pistachio-reset.txt | 1 Pistachio Reset Controller
4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
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| D | amlogic,meson-reset.yaml | 5 $id: "http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#"
8 title: Amlogic Meson SoC Reset Controller
16 - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
17 - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
18 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
23 "#reset-cells":
29 - "#reset-cells"
33 reset-controller@c884404 {
34 compatible = "amlogic,meson-gxbb-reset";
36 #reset-cells = <1>;
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| D | brcm,brcmstb-reset.txt | 1 Broadcom STB SW_INIT-style reset controller
4 Broadcom STB SoCs have a SW_INIT-style reset controller with separate
6 reset lines.
8 Please also refer to reset.txt in this directory for common reset
12 - compatible: should be brcm,brcmstb-reset
14 - #reset-cells: must be set to 1
18 reset: reset-controller@8404318 {
19 compatible = "brcm,brcmstb-reset";
21 #reset-cells = <1>;
25 resets = <&reset 26>;
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| D | ath79-reset.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9XXX reset controller
3 Please also refer to reset.txt in this directory for common reset
7 - compatible: has to be "qca,<soctype>-reset", "qca,ar7100-reset"
10 - #reset-cells : Specifies the number of cells needed to encode reset
15 reset-controller@1806001c {
16 compatible = "qca,ar9132-reset", "qca,ar7100-reset";
19 #reset-cells = <1>;
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| D | hisilicon,hi3660-reset.txt | 1 Hisilicon System Reset Controller
4 Please also refer to reset.txt in this directory for common reset
7 The reset controller registers are part of the system-ctl block on
12 "hisilicon,hi3660-reset" for HI3660
13 "hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670
14 - hisi,rst-syscon: phandle of the reset's syscon.
15 - #reset-cells : Specifies the number of cells needed to encode a
16 reset source. The type shall be a <u32> and the value shall be 2.
18 Cell #1 : offset of the reset assert control
22 Cell #2 : bit position of the reset in the reset control register
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| D | ti,sci-reset.txt | 1 Texas Instruments System Control Interface (TI-SCI) Reset Controller
12 TI-SCI Reset Controller Node
14 This reset controller node uses the TI SCI protocol to perform the reset
20 - compatible : Should be "ti,sci-reset"
21 - #reset-cells : Should be 2. Please see the reset consumer node below for
24 TI-SCI Reset Consumer Nodes
26 Each of the reset consumer nodes should have the following properties,
31 - resets : A phandle and reset specifier pair, one pair for each reset
33 The phandle should point to the TI-SCI reset controller node,
34 and the reset specifier should have 2 cell-values. The first
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| D | snps,dw-reset.txt | 1 Synopsys DesignWare Reset controller
4 Please also refer to reset.txt in this directory for common reset
10 "snps,dw-high-reset" - for active high configuration
11 "snps,dw-low-reset" - for active low configuration
16 - #reset-cells: must be 1.
20 dw_rst_1: reset-controller@0000 {
21 compatible = "snps,dw-high-reset";
23 #reset-cells = <1>;
26 dw_rst_2: reset-controller@1000 {i
27 compatible = "snps,dw-low-reset";
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| D | oxnas,reset.txt | 1 Oxford Semiconductor OXNAS SoC Family RESET Controller
4 Please also refer to reset.txt in this directory for common reset
8 - compatible: For OX810SE, should be "oxsemi,ox810se-reset"
9 For OX820, should be "oxsemi,ox820-reset"
10 - #reset-cells: 1, see below
18 Reset indices are in dt-bindings include files :
19 - For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h
20 - For OX820: include/dt-bindings/reset/oxsemi,ox820.h
28 reset: reset-controller {
29 compatible = "oxsemi,ox810se-reset";
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| D | xlnx,zynqmp-reset.txt | 2 = Zynq UltraScale+ MPSoC reset driver binding =
9 Please also refer to reset.txt in this directory for common reset
13 - compatible: "xlnx,zynqmp-reset"
14 - #reset-cells: Specifies the number of cells needed to encode reset
26 zynqmp_reset: reset-controller {
27 compatible = "xlnx,zynqmp-reset";
28 #reset-cells = <1>;
33 Specifying reset lines connected to IP modules
36 Device nodes that need access to reset lines should
37 specify them as a reset phandle in their corresponding node as
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| D | qcom,aoss-reset.txt | 1 Qualcomm AOSS Reset Controller
4 This binding describes a reset-controller found on AOSS-CC (always on subsystem)
20 - #reset-cells:
23 Definition: must be 1; cell entry represents the reset index.
27 aoss_reset: reset-controller@c2a0000 {
30 #reset-cells = <1>;
33 Specifying reset lines connected to IP modules
36 Device nodes that need access to reset lines should
37 specify them as a reset phandle in their corresponding node as
38 specified in reset.txt.
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| D | qcom,pdc-global.txt | 4 This binding describes a reset-controller found on PDC-Global (Power Domain
20 - #reset-cells:
23 Definition: must be 1; cell entry represents the reset index.
27 pdc_reset: reset-controller@b2e0000 {
30 #reset-cells = <1>;
33 PDC reset clients
36 Device nodes that need access to reset lines should
37 specify them as a reset phandle in their corresponding node as
38 specified in reset.txt.
40 For a list of all valid reset indices see
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| D | berlin,reset.txt | 1 Marvell Berlin reset controller
4 Please also refer to reset.txt in this directory for common reset
7 The reset controller node must be a sub-node of the chip controller
11 - compatible: should be "marvell,berlin2-reset"
12 - #reset-cells: must be set to 2
16 chip_rst: reset {
17 compatible = "marvell,berlin2-reset";
18 #reset-cells = <2>;
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| D | bitmain,bm1880-reset.txt | 1 Bitmain BM1880 SoC Reset Controller
4 Please also refer to reset.txt in this directory for common reset
8 - compatible: Should be "bitmain,bm1880-reset"
9 - reg: Offset and length of reset controller space in SCTRL.
10 - #reset-cells: Must be 1.
14 rst: reset-controller@c00 {
15 compatible = "bitmain,bm1880-reset";
17 #reset-cells = <1>;
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| D | sirf,rstc.txt | 1 CSR SiRFSoC Reset Controller
4 Please also refer to reset.txt in this directory for common reset
11 - #reset-cells: 1, see below
15 rstc: reset-controller@88010000 {
18 #reset-cells = <1>;
21 Specifying reset lines connected to IP modules
24 The reset controller(rstc) manages various reset sources. This module provides
25 reset signals for most blocks in system. Those device nodes should specify the
26 reset line on the rstc in their resets property, containing a phandle to the
27 rstc device node and a RESET_INDEX specifying which module to reset, as described
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| D | zte,zx2967-reset.txt | 1 ZTE zx2967 SoCs Reset Controller
4 Please also refer to reset.txt in this directory for common reset
9 * zte,zx296718-reset
12 - #reset-cells: must be 1.
16 reset: reset-controller@1461060 {
17 compatible = "zte,zx296718-reset";
19 #reset-cells = <1>;
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| D | allwinner,sunxi-clock-reset.txt | 1 Allwinner sunxi Peripheral Reset Controller
4 Please also refer to reset.txt in this directory for common reset
9 "allwinner,sun6i-a31-ahb1-reset"
10 "allwinner,sun6i-a31-clock-reset"
13 - #reset-cells: 1, see below
17 ahb1_rst: reset@1c202c0 {
18 #reset-cells = <1>;
19 compatible = "allwinner,sun6i-a31-ahb1-reset";
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| /Documentation/devicetree/bindings/power/reset/ |
| D | keystone-reset.txt | 1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
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| /Documentation/devicetree/bindings/power/ |
| D | amlogic,meson-gx-pwrc.txt | 24 - resets: phandles to the reset lines needed for this power demain sequence
25 as described in ../reset/reset.txt
45 resets = <&reset RESET_VIU>,
46 <&reset RESET_VENC>,
47 <&reset RESET_VCBUS>,
48 <&reset RESET_BT656>,
49 <&reset RESET_DVIN_RESET>,
50 <&reset RESET_RDMA>,
51 <&reset RESET_VENCI>,
52 <&reset RESET_VENCP>,
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