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/Documentation/devicetree/bindings/mfd/
Dmc13xxx.txt16 - leds : Contain the led nodes and initial register values in property
17 "led-control". Number of register depends of used IC, for MC13783 is 6,
55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
59 sw3 : regulator SW3 (register 29, bit 20)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
[all …]
/Documentation/scsi/
Dhptiop.txt3 Controller Register Map
8 BAR0 offset Register
12 BAR2 offset Register
13 0x10 Inbound Message Register 0
14 0x14 Inbound Message Register 1
15 0x18 Outbound Message Register 0
16 0x1C Outbound Message Register 1
17 0x20 Inbound Doorbell Register
18 0x24 Inbound Interrupt Status Register
19 0x28 Inbound Interrupt Mask Register
[all …]
/Documentation/devicetree/bindings/leds/
Dregister-bit-led.txt1 Device Tree Bindings for Register Bit LEDs
3 Register bit leds are used with syscon multifunctional devices
4 where single bits in a certain register can turn on/off a
5 single LED. The register bit LEDs appear as children to the
16 - compatible : must be "register-bit-led"
17 - offset : register offset to the register controlling this LED
18 - mask : bit mask for the bit controlling this LED in the register
36 compatible = "register-bit-led";
44 compatible = "register-bit-led";
52 compatible = "register-bit-led";
[all …]
/Documentation/devicetree/bindings/power/reset/
Dsyscon-poweroff.txt1 Generic SYSCON mapped register poweroff driver
3 This is a generic poweroff driver using syscon to map the poweroff register.
4 The poweroff is generally performed with a write to the poweroff register
5 defined by the register map pointed by syscon reference plus the offset
10 - regmap: this is phandle to the register map node
11 - offset: offset in the register map for the poweroff register (in bytes)
12 - value: the poweroff value written to the poweroff register (32 bit access)
15 - mask: update only the register bits defined by the mask (32 bit)
Dsyscon-reboot.txt1 Generic SYSCON mapped register reset driver
3 This is a generic reset driver using syscon to map the reset register.
4 The reset is generally performed with a write to the reset register
5 defined by the register map pointed by syscon reference plus the offset
10 - regmap: this is phandle to the register map node
11 - offset: offset in the register map for the reboot register (in bytes)
12 - value: the reset value written to the reboot register (32 bit access)
15 - mask: update only the register bits defined by the mask (32 bit)
/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-tmc15 The value is read directly from HW register RSZ, 0x004.
21 Description: (R) Shows the value held by the TMC status register. The value
22 is read directly from HW register STS, 0x00C.
28 Description: (R) Shows the value held by the TMC RAM Read Pointer register
30 interface. The value is read directly from HW register RRP,
37 Description: (R) Shows the value held by the TMC RAM Write Pointer register
40 from HW register RWP, 0x018.
47 read directly from HW register TRG, 0x01C.
53 Description: (R) Shows the value held by the TMC Control register. The value
54 is read directly from HW register CTL, 0x020.
[all …]
Dsysfs-bus-coresight-devices-etb1017 value stored in this register+1 (from ARM ETB-TRM).
24 2. The value is read directly from HW register RDP, 0x004.
30 Description: (R) Shows the value held by the ETB status register. The value
31 is read directly from HW register STS, 0x00C.
37 Description: (R) Shows the value held by the ETB RAM Read Pointer register
39 interface. The value is read directly from HW register RRP,
46 Description: (R) Shows the value held by the ETB RAM Write Pointer register
49 from HW register RWP, 0x018.
56 read directly from HW register TRG, 0x01C.
62 Description: (R) Shows the value held by the ETB Control register. The value
[all …]
/Documentation/devicetree/bindings/c6x/
Ddscr.txt9 more configuration registers often protected by a lock register where one or
10 more key values must be written to a lock register in order to unlock the
11 configuration register for writes. These configuration register may be used to
13 sources (internal or pin), etc. In some cases, a configuration register is
25 - reg: register area base and size
35 offset of the devstat register
46 a lock register. Each tuple consists of the register offset, lock register
47 offsset, and the key value used to unlock the register.
52 written to the first kick register and the second key must be written to
53 the second register before other registers in the area are write-enabled.
[all …]
/Documentation/hwmon/
Ducd9200.rst62 in1_input Measured voltage. From READ_VIN register.
63 in1_min Minimum Voltage. From VIN_UV_WARN_LIMIT register.
64 in1_max Maximum voltage. From VIN_OV_WARN_LIMIT register.
65 in1_lcrit Critical minimum Voltage. VIN_UV_FAULT_LIMIT register.
67 register.
74 in[2-5]_input Measured voltage. From READ_VOUT register.
75 in[2-5]_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register.
76 in[2-5]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
77 in[2-5]_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
79 register.
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Dmax8688.rst49 in1_input Measured voltage. From READ_VOUT register.
50 in1_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register.
51 in1_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
52 in1_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
54 register.
65 curr1_input Measured current. From READ_IOUT register.
66 curr1_max Maximum current. From IOUT_OC_WARN_LIMIT register.
68 register.
69 curr1_max_alarm Current high alarm. From IOUT_OC_WARN_LIMIT register.
74 temp1_input Measured temperature. From READ_TEMPERATURE_1 register.
[all …]
Dpmbus.rst94 This driver does not probe for PMBus devices, since there is no register
95 which can be safely used to identify the chip (The MFG_ID register is not
188 inX_input Measured voltage. From READ_VIN or READ_VOUT register.
190 From VIN_UV_WARN_LIMIT or VOUT_UV_WARN_LIMIT register.
192 From VIN_OV_WARN_LIMIT or VOUT_OV_WARN_LIMIT register.
194 From VIN_UV_FAULT_LIMIT or VOUT_UV_FAULT_LIMIT register.
196 From VIN_OV_FAULT_LIMIT or VOUT_OV_FAULT_LIMIT register.
205 currX_input Measured current. From READ_IIN or READ_IOUT register.
207 From IIN_OC_WARN_LIMIT or IOUT_OC_WARN_LIMIT register.
209 From IOUT_UC_FAULT_LIMIT register.
[all …]
/Documentation/devicetree/bindings/reset/
Dti-syscon-reset.txt7 sometimes a part of a larger register space region implementing various
8 functionalities. This register range is best represented as a syscon node to
10 register space.
30 - ti,reset-bits : Contains the reset control register information
34 register from the syscon register base
36 assert control register
38 register from the syscon register base
40 deassert control register
41 Cell #5 : offset of the reset status register
42 from the syscon register base
[all …]
/Documentation/devicetree/bindings/sound/
Dalc5623.txt10 - add-ctrl: Default register value for Reg-40h, Additional Control
11 Register. If absent or has the value of 0, the
12 register is untouched.
14 - jack-det-ctrl: Default register value for Reg-5Ah, Jack Detect
15 Control Register. If absent or has value 0, the
16 register is untouched.
/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-single.txt1 One-register-per-pin type device tree based pinctrl driver
8 - reg : offset and length of the register set for the mux registers
13 - pinctrl-single,register-width : pinmux register access width in bits
16 in the pinmux register
23 - pinctrl-single,bit-per-mux : boolean to indicate that one register controls
28 drive strength in the pinmux register. They're value of drive strength
35 input bias pullup in the pinmux register.
41 input bias pulldown in the pinmux register.
57 input schmitt in the pinmux register. In some silicons, there're two input
58 schmitt value (rising-edge & falling-edge) in the pinmux register.
[all …]
/Documentation/devicetree/bindings/arm/
Drenesas,prr.txt1 Renesas Product Register
3 Most Renesas ARM SoCs have a Product Register or Boundary Scan ID Register that
5 node for this register should be added.
11 - reg: Base address and length of the register block.
/Documentation/devicetree/bindings/clock/ti/
Dmux.txt6 register-mapped multiplexer with multiple input clock signals or
15 results in programming the register as follows:
17 register value selected parent clock
23 into the register, instead indexing begins at 1. The optional property
26 register value selected clock parent
31 The binding must provide the register to control the mux. Optionally
32 the number of bits to shift the control field in the register can be
42 - reg : register offset for register controlling adjustable mux
51 - ti,latch-bit : latch the mux value to HW, only needed if the register
/Documentation/driver-api/mmc/
Dmmc-dev-attrs.rst20 cid Card Identification Register
21 csd Card Specific Data Register
22 scr SD Card Configuration Register (SD only)
23 date Manufacturing Date (from CID Register)
24 fwrev Firmware/Product Revision (from CID Register)
26 hwrev Hardware/Product Revision (from CID Register)
28 manfid Manufacturer ID (from CID Register)
29 name Product Name (from CID Register)
30 oemid OEM/Application ID (from CID Register)
31 prv Product Revision (from CID Register)
[all …]
/Documentation/devicetree/bindings/i2c/
Di2c-mux-reg.txt1 Register-based I2C Bus Mux
3 This binding describes an I2C bus multiplexer that uses a single register
14 - reg: this pair of <offset size> specifies the register to control the mux.
18 - little-endian: The existence indicates the register is in little endian.
19 - big-endian: The existence indicates the register is in big endian.
22 - write-only: The existence indicates the register is write-only.
27 in the relevant node's reg property will be output to the register.
31 register will be set according to the idle value.
34 left programmed into the register.
45 little-endian; /* little endian register on PCIe */
/Documentation/devicetree/bindings/mmc/
Dsdhci.txt7 - sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
8 property corresponds to the bits in the sdhci capability register. If the bit
9 is on in the mask then the bit is incorrect in the register and should be
11 - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
12 property corresponds to the bits in the sdhci capability register. If the
/Documentation/devicetree/bindings/net/
Dmicrel.txt12 KSZ8001: register 0x1e, bits 15..14
13 KSZ8041: register 0x1e, bits 15..14
14 KSZ8021: register 0x1f, bits 5..4
15 KSZ8031: register 0x1f, bits 5..4
16 KSZ8051: register 0x1f, bits 5..4
17 KSZ8081: register 0x1f, bits 5..4
18 KSZ8091: register 0x1f, bits 5..4
/Documentation/devicetree/bindings/regulator/
Danatop-regulator.txt6 - anatop-reg-offset: Anatop MFD register offset
7 - anatop-vol-bit-shift: Bit shift for the register
8 - anatop-vol-bit-width: Number of bits used in the register
9 - anatop-min-bit-val: Minimum value of this register
14 - anatop-delay-reg-offset: Anatop MFD step time register offset
15 - anatop-delay-bit-shift: Bit shift for the step time register
16 - anatop-delay-bit-width: Number of bits used in the step time register
/Documentation/devicetree/bindings/phy/
Dti-phy.txt7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
39 - reg : Address and length of the register set for the device.
54 module and the register offset to power on/off the PHY.
72 - reg : Address and length of the register set for the device.
73 - reg-names: The names of the register addresses corresponding to the registers
93 CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
[all …]
/Documentation/devicetree/bindings/rtc/
Drtc-meson-vrtc.txt4 virtual from a Linux perspective. The interface is 1 register where
9 - reg: physical address for the alarm register
11 The alarm register is a simple scratch register shared between the
13 the AP suspends, the SCP will use the value of this register to
/Documentation/virt/kvm/devices/
Darm-vgic.txt23 register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2.
28 interface register mappings. Only valid for KVM_DEV_TYPE_ARM_VGIC_V2.
47 GICv2 specs. Getting or setting such a register has the same effect as
48 reading or writing the register on the actual hardware from the cpu whose
51 vcpu_index used to access the register.
62 -ENXIO: Getting or setting this register is not yet supported
75 defined in the GICv2 specs. Getting or setting such a register has the
76 same effect as reading or writing the register on the actual hardware.
81 guest. This interface always exposes four register APR[0-3] describing the
82 maximum possible 128 preemption levels. The semantics of the register
[all …]
/Documentation/devicetree/bindings/display/imx/
Dfsl,imx-fb.txt7 - reg : Should contain 1 register ranges(address and length)
21 - fsl,dmacr: DMA Control Register value. This is optional. By default, the
22 register is not modified as recommended by the datasheet.
23 - fsl,lpccr: Contrast Control Register value. This property provides the
24 default value for the contrast control register.
25 If that property is omitted, the register is zeroed.
26 - fsl,lscr1: LCDC Sharp Configuration Register value.

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