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/Documentation/devicetree/bindings/arm/amlogic/
Dsmp-sram.txt1 Amlogic Meson8 and Meson8b SRAM for smp bringup:
4 Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
13 "amlogic,meson8-smp-sram"
14 "amlogic,meson8b-smp-sram"
28 smp-sram@1ff80 {
29 compatible = "amlogic,meson8b-smp-sram";
/Documentation/devicetree/bindings/sram/
Drockchip-smp-sram.txt1 Rockchip SRAM for smp bringup:
4 Rockchip's smp-capable SoCs use the first part of the sram for the bringup
12 - compatible : should be "rockchip,rk3066-smp-sram"
26 smp-sram@10080000 {
27 compatible = "rockchip,rk3066-smp-sram";
Dmilbeaut-smp-sram.txt1 Milbeaut SRAM for smp bringup
9 - compatible : should be "socionext,milbeaut-smp-sram"
20 smp-sram@f100 {
21 compatible = "socionext,milbeaut-smp-sram";
Drenesas,smp-sram.txt1 * Renesas SMP SRAM
9 - compatible: Must be "renesas,smp-sram",
23 smp-sram@0 {
24 compatible = "renesas,smp-sram";
Dsamsung-sram.txt1 Samsung Exynos SYSRAM for SMP bringup:
4 Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
29 smp-sysram@0 {
34 smp-sysram@53000 {
Dsram.txt66 smp-sram@100 {
67 compatible = "socvendor,smp-sram";
/Documentation/devicetree/bindings/arm/cpu-enable-method/
Dmarvell,berlin-smp2 Secondary CPU enable-method "marvell,berlin-smp" binding
5 This document describes the "marvell,berlin-smp" method for enabling secondary
6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
9 Enable method name: "marvell,berlin-smp"
23 enable-method = "marvell,berlin-smp";
Dal,alpine-smp2 Secondary CPU enable-method "al,alpine-smp" binding
5 This document describes the "al,alpine-smp" method for
7 "al,alpine-smp" enable method should be defined in the
10 Enable method name: "al,alpine-smp"
45 enable-method = "al,alpine-smp";
Dnuvoton,npcm750-smp2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
22 enable-method = "nuvoton,npcm750-smp";
/Documentation/devicetree/bindings/arm/sunxi/
Dsmp-sram.txt1 Allwinner SRAM for smp bringup:
21 "allwinner,sun9i-a80-smp-sram"
36 smp-sram@1000 {
39 * cpu0 should jump to SMP entry vector
41 compatible = "allwinner,sun9i-a80-smp-sram";
/Documentation/devicetree/bindings/arm/
Dcpus.yaml172 - actions,s500-smp
175 - allwinner,sun9i-a80-smp
176 - allwinner,sun8i-a83t-smp
177 - amlogic,meson8-smp
178 - amlogic,meson8b-smp
179 - arm,realview-smp
180 - aspeed,ast2600-smp
183 - brcm,bcm2836-smp
185 - brcm,bcm-nsp-smp
187 - marvell,armada-375-smp
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dcsky,mpintc.txt6 SMP soc, and it also could be used in non-SMP system.
23 Description: Describes SMP interrupt controller
Dbrcm,bcm7038-l1-intc.txt34 If multiple reg ranges and interrupt-parent entries are present on an SMP
35 system, the driver will allow IRQ SMP affinity to be set up through the
Dbrcm,bcm6345-l1-intc.txt35 If multiple reg ranges and interrupt-parent entries are present on an SMP
36 system, the driver will allow IRQ SMP affinity to be set up through the
/Documentation/devicetree/bindings/clock/
Dux500.txt30 - smp-twd-clock: a subnode for the ARM SMP Timer Watchdog cluster
61 smp_twd_clk: smp-twd-clock {
/Documentation/devicetree/bindings/arm/omap/
Dmpu.txt25 - For an OMAP5 SMP system:
32 - For an OMAP4 SMP system:
/Documentation/x86/i386/
DIO-APIC.rst9 Most (all) Intel-MP compliant SMP boards have the so-called 'IO-APIC',
15 Linux supports all variants of compliant SMP boards, including ones with
20 usually worked around by the kernel. If your MP-compliant SMP board does
21 not boot Linux, then consult the linux-smp mailing list archives first.
120 Good luck and mail to linux-smp@vger.kernel.org or
/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,nsp-cpu-method.txt9 - enable-method = "brcm,bcm-nsp-smp";
35 enable-method = "brcm,bcm-nsp-smp";
/Documentation/devicetree/bindings/timer/
Dcsky,mptimer.txt5 C-SKY multi-processors timer is designed for C-SKY SMP system and the
17 Description: Describes SMP timer
Dsnps,archs-gfrc.txt2 - clocksource provider for SMP SoC
/Documentation/devicetree/bindings/csky/
Dcpus.txt9 Only SMP system need to care about the cpus node and single processor
35 Description: Describes one of SMP cores
/Documentation/scsi/
Dlibsas.txt366 implements an SMP portal (Note: this is *NOT* an SMP port),
367 to which user space applications can send SMP requests and
368 receive SMP responses.
372 1. Build the SMP frame you want to send. The format and layout
375 2. Open the expander's SMP portal sysfs file in RW mode.
390 argument, the sysfs file name of the SMP portal to the
394 The SMP portal gives you complete control of the expander,
/Documentation/scheduler/
Dsched-domains.rst60 In SMP, the parent of the base domain will span all physical CPUs in the
62 of the SMP domain will span the entire machine, with each group having the
72 retain the traditional SMT->SMP->NUMA topology (or some subset of that). This
/Documentation/admin-guide/
Dtainted-kernels.rst29 Oops: 0002 [#1] SMP PTI
87 2 _/S 4 SMP kernel oops on an officially SMP incapable processor
119 2) ``S`` if the oops occurred on an SMP kernel running on hardware that
122 SMP capable.
/Documentation/
DIRQ-affinity.txt2 SMP IRQ affinity
22 it to CPU4-7 (this is an 8-CPU SMP box)::

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