Searched full:spis (Results 1 – 10 of 10) sorted by relevance
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | al,alpine-msix.txt | 13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
24 al,msi-num-spis = <160>;
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| D | socionext,synquacer-exiu.txt | 5 level-high type GICv3 SPIs.
20 - Only SPIs can use the EXIU as an interrupt parent.
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| D | arm,gic.yaml | 70 2 = high-to-low edge triggered (invalid for SPIs)
72 8 = active low level-sensitive (invalid for SPIs).
157 arm,msi-num-spis:
159 this property should contain the number of SPIs assigned to the
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| D | ti,omap4-wugen-mpu | 20 - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
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| D | nvidia,tegra20-ictlr.txt | 27 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | img,pistachio-pinctrl.txt | 64 mfio11 spis
65 mfio12 spis
66 mfio13 spis
67 mfio14 spis
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| /Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 52 When using SPIs, specifies a list of phandles to CPU
54 the SPIs listed in the interrupts property.
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 19 to deliver its interrupts via SPIs.
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| D | arm,arch_timer_mmio.yaml | 17 The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
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| /Documentation/virt/kvm/devices/ |
| D | arm-vgic-v3.txt | 242 PPIs are reported per VCPU as specified in the mpidr field, and SPIs are
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