Searched full:sifive (Results 1 – 14 of 14) sorted by relevance
| /Documentation/devicetree/bindings/spi/ |
| D | spi-sifive.txt | 1 SiFive SPI controller Device Tree Bindings
5 - compatible : Should be "sifive,<chip>-spi" and "sifive,spi<version>".
7 "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
8 onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
10 Please refer to sifive-blocks-ip-versioning.txt for details
20 - sifive,fifo-depth : Depth of hardware queues; defaults to 8
21 - sifive,max-bits-per-word : Maximum bits per word; defaults to 8
24 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
28 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
35 sifive,fifo-depth = <8>;
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| /Documentation/devicetree/bindings/serial/ |
| D | sifive-serial.yaml | 4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
20 - const: sifive,fu540-c000-uart
21 - const: sifive,uart0
24 Should be something similar to "sifive,<chip>-uart"
26 and "sifive,uart<version>" for the general UART IP
32 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
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| /Documentation/devicetree/bindings/pwm/ |
| D | pwm-sifive.txt | 1 SiFive PWM controller
3 Unlike most other PWM controllers, the SiFive PWM controller currently only
10 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
13 - compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
14 Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
15 PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
16 SiFive PWM v0 IP block with no chip integration tweaks.
17 Please refer to sifive-blocks-ip-versioning.txt for details.
27 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
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| /Documentation/devicetree/bindings/sifive/ |
| D | sifive-blocks-ip-versioning.txt | 1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
23 "sifive,uart0" to indicate that their driver is compatible with the
25 upstream sifive-blocks commits. It is expected that most drivers will
30 "sifive,fu540-c000-uart". This way, if SoC-specific
33 IP block-specific compatible string (such as "sifive,uart0") should
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| /Documentation/devicetree/bindings/riscv/ |
| D | sifive.yaml | 4 $id: http://devicetree.org/schemas/riscv/sifive.yaml#
7 title: SiFive SoC-based boards
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 SiFive SoC-based boards
22 - sifive,hifive-unleashed-a00
23 - const: sifive,fu540-c000
24 - const: sifive,fu540
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| D | cpus.yaml | 10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
30 - sifive,rocket0
31 - sifive,e5
32 - sifive,e51
33 - sifive,u54-mc
34 - sifive,u54
35 - sifive,u5
98 // Example 1: SiFive Freedom U540G Development Kit
105 compatible = "sifive,rocket0", "riscv";
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| D | sifive-l2-cache.txt | 1 SiFive L2 Cache Controller
3 The SiFive Level 2 Cache Controller is used to provide access to fast copies
10 - compatible: Should be "sifive,fu540-c000-ccache" and "cache"
40 compatible = "sifive,fu540-c000-ccache", "cache";
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.txt | 1 SiFive Platform-Level Interrupt Controller (PLIC)
4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
26 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
28 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
31 - compatible : "sifive,plic-1.0.0" and a string identifying the actual
48 compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";
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| D | riscv,cpu-intc.txt | 49 compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";
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| /Documentation/devicetree/bindings/clock/sifive/ |
| D | fu540-prci.txt | 1 SiFive FU540 PRCI bindings
7 - compatible: Should be "sifive,<chip>-prci". Only one value is
8 supported: "sifive,fu540-c000-prci"
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
42 compatible = "sifive,fu540-c000-prci";
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| /Documentation/devicetree/bindings/net/ |
| D | macb.txt | 18 Use "sifive,fu540-c000-gem" for SiFive FU540-C000 SoC.
21 For "sifive,fu540-c000-gem", second range is required to specify the
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-ocores.txt | 6 "sifive,fu540-c000-i2c", "sifive,i2c0"
8 FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 497 compatible = "sifive,fu540g", "sifive,fu500";
498 model = "sifive,hifive-unleashed-a00";
525 compatible = "sifive,rocket0", "riscv";
531 compatible = "sifive,rocket0", "riscv";
536 compatible = "sifive,rocket0", "riscv";
541 compatible = "sifive,rocket0", "riscv";
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| /Documentation/devicetree/bindings/ |
| D | vendor-prefixes.yaml | 850 "^sifive,.*":
851 description: SiFive, Inc.
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