Searched +full:soc +full:- +full:based (Results 1 – 25 of 157) sorted by relevance
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| /Documentation/devicetree/bindings/ptp/ |
| D | brcm,ptp-dte.txt | 1 * Broadcom Digital Timing Engine(DTE) based PTP clock
4 - compatible: should contain the core compatibility string
5 and the SoC compatibility string. The SoC
6 compatibility string is to handle SoC specific
9 "brcm,ptp-dte"
10 SoC compatibility strings:
11 "brcm,iproc-ptp-dte" - for iproc based SoC's
12 - reg: address and length of the DTE block's NCO registers
16 ptp: ptp-dte@180af650 {
17 compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
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| /Documentation/arm/spear/ |
| D | overview.rst | 6 ------------
11 The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
19 - SPEAr3XX (3XX SOC series, based on ARM9)
20 - SPEAr300 (SOC)
21 - SPEAr300 Evaluation Board
22 - SPEAr310 (SOC)
23 - SPEAr310 Evaluation Board
24 - SPEAr320 (SOC)
25 - SPEAr320 Evaluation Board
26 - SPEAr6XX (6XX SOC series, based on ARM9)
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| /Documentation/devicetree/bindings/riscv/ |
| D | sifive.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive SoC-based boards
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 SiFive SoC-based boards
21 - enum:
22 - sifive,hifive-unleashed-a00
23 - const: sifive,fu540-c000
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| /Documentation/devicetree/bindings/rtc/ |
| D | isil,isl12057.txt | 8 ("wakeup-source") to handle the specific use-case found
9 on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104
10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip
12 to the SoC but to a PMIC. It allows the device to be powered up when
15 be set when the IRQ#2 pin of the chip is not connected to the SoC but
20 - "compatible": must be "isil,isl12057"
21 - "reg": I2C bus address of the device
25 - "wakeup-source": mark the chip as a wakeup source, independently of
26 the availability of an IRQ line connected to the SoC.
37 Example isl12057 node with IRQ#2 pin connected to main SoC via MPP6 (note
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| D | rtc-mt7622.txt | 1 Device-Tree bindings for MediaTek SoC based RTC
4 - compatible : Should be
5 "mediatek,mt7622-rtc", "mediatek,soc-rtc" : for MT7622 SoC
6 - reg : Specifies base physical address and size of the registers;
7 - interrupts : Should contain the interrupt for RTC alarm;
8 - clocks : Specifies list of clock specifiers, corresponding to
9 entries in clock-names property;
10 - clock-names : Should contain "rtc" entries
15 compatible = "mediatek,mt7622-rtc",
16 "mediatek,soc-rtc";
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| /Documentation/devicetree/bindings/arm/samsung/ |
| D | samsung-boards.txt | 1 * Samsung's Exynos and S5P SoC based boards
4 - compatible = should be one or more of the following.
5 - "samsung,aries" - for S5PV210-based Samsung Aries board.
6 - "samsung,fascinate4g" - for S5PV210-based Samsung Galaxy S Fascinate 4G (SGH-T959P) board.
7 - "samsung,galaxys" - for S5PV210-based Samsung Galaxy S (i9000) board.
8 - "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
9 - "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
10 - "samsung,monk" - for Exynos3250-based Samsung Simband board.
11 - "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
12 - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
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| D | sysreg.txt | 1 SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
4 - compatible : should contain two values. First value must be one from following list:
5 - "samsung,exynos4-sysreg" - for Exynos4 based SoCs,
6 - "samsung,exynos5-sysreg" - for Exynos5 based SoCs.
8 - reg : offset and length of the register set.
12 compatible = "samsung,exynos4-sysreg", "syscon";
17 compatible = "samsung,exynos5-sysreg", "syscon";
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| /Documentation/arm/keystone/ |
| D | overview.rst | 6 ------------
7 Keystone range of SoCs are based on ARM Cortex-A15 MPCore Processors
9 for users to run Linux on Keystone based EVMs from Texas Instruments.
11 Following SoCs & EVMs are currently supported:-
13 K2HK SoC and EVM
16 a.k.a Keystone 2 Hawking/Kepler SoC
23 http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
25 K2E SoC and EVM
28 a.k.a Keystone 2 Edison SoC
30 K2E - 66AK2E05:
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| /Documentation/devicetree/bindings/arm/ti/ |
| D | k3.txt | 1 Texas Instruments K3 Multicore SoC architecture device tree bindings
2 --------------------------------------------------------------------
4 Platforms based on Texas Instruments K3 Multicore SoC architecture
8 ----
10 Each device tree root node must specify which exact SoC in K3 Multicore SoC
13 - AM654
16 - J721E
20 ------
23 of the following board-specific compatible values:
25 - AM654 EVM
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| /Documentation/devicetree/bindings/gpu/ |
| D | samsung-g2d.txt | 4 - compatible : value should be one among the following:
5 (a) "samsung,s5pv210-g2d" for G2D IP present in S5PV210 & Exynos4210 SoC
6 (b) "samsung,exynos4212-g2d" for G2D IP present in Exynos4x12 SoCs
7 (c) "samsung,exynos5250-g2d" for G2D IP present in Exynos5250 SoC
9 - reg : Physical base address of the IP registers and length of memory
12 - interrupts : G2D interrupt number to the CPU.
13 - clocks : from common clock binding: handle to G2D clocks.
14 - clock-names : names of clocks listed in clocks property, in the same
15 order, depending on SoC type:
16 - for S5PV210 and Exynos4 based SoCs: "fimg2d" and
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| /Documentation/devicetree/bindings/mfd/ |
| D | twl-familly.txt | 10 - compatible : Must be "ti,twl4030";
11 For Integrated power-management/audio CODEC device used in OMAP3
12 based boards
13 - compatible : Must be "ti,twl6030";
14 For Integrated power-management used in OMAP4 based boards
15 - interrupts : This i2c device has an IRQ line connected to the main SoC
16 - interrupt-controller : Since the twl support several interrupts internally,
17 it is considered as an interrupt controller cascaded to the SoC one.
18 - #interrupt-cells = <1>;
21 - Child nodes contain in the twl. The twl family is made of several variants
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| /Documentation/devicetree/bindings/arm/ |
| D | qcom.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@codeaurora.org>
13 Some qcom based bootloaders identify the dtb blob based on a set of
14 device properties like SoC and platform and revisions of those components.
18 Each board must specify a top-level board compatible string with the following
21 compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"
23 The 'SoC' and 'board' elements are required. All other elements are optional.
25 The 'SoC' element must be one of the following strings:
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| D | amlogic,scpi.txt | 3 ----------------------------------------------------------
6 - compatible : should be "amlogic,meson-gxbb-scpi"
9 ------------------------------------
12 - compatible : should be "amlogic,meson-gxbb-sram"
14 Each sub-node represents the reserved area for SCPI.
16 Required sub-node properties:
17 - compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared
18 memory on Amlogic GXBB SoC.
20 Sensor bindings for the sensors based on SCPI Message Protocol
21 --------------------------------------------------------------
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| D | calxeda.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
12 Bindings for boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC
13 or Cortex-A15 based ECX-2000 SOCs
20 - enum:
21 - calxeda,highbank
22 - calxeda,ecx-2000
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | brcm,iproc-gpio.txt | 5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
8 based SoCs
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
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| /Documentation/devicetree/bindings/arm/keystone/ |
| D | keystone.txt | 2 -----------------------------------------------
4 Boards with Keystone2 based devices (TCI66xxK2H) SOC shall have the
8 - compatible: All TI specific devices present in Keystone SOC should be in
9 the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
12 SoC families:
14 - Keystone 2 generic SoC:
19 - Keystone 2 Hawking/Kepler
21 - Keystone 2 Lamarr
23 - Keystone 2 Edison
25 - K2G
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| /Documentation/devicetree/bindings/reset/ |
| D | amlogic,meson-axg-audio-arb.txt | 4 disables the access of Audio FIFOs to DDR on AXG based SoC.
7 - compatible: 'amlogic,meson-axg-audio-arb'
8 - reg: physical base address of the controller and length of memory
10 - clocks: phandle to the fifo peripheral clock provided by the audio
12 - #reset-cells: must be 1.
14 Example on the A113 SoC:
16 arb: reset-controller@280 {
17 compatible = "amlogic,meson-axg-audio-arb";
19 #reset-cells = <1>;
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| /Documentation/devicetree/bindings/spi/ |
| D | qcom,spi-geni-qcom.txt | 1 GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
3 The QUP v3 core is a GENI based AHB slave that provides a common data path
5 mini-core.
11 - compatible: Must contain "qcom,geni-spi".
12 - reg: Must contain SPI register location and length.
13 - interrupts: Must contain SPI controller interrupts.
14 - clock-names: Must contain "se".
15 - clocks: Serial engine core clock needed by the device.
16 - #address-cells: Must be <1> to define a chip select address on
18 - #size-cells: Must be <0>.
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| /Documentation/devicetree/bindings/security/tpm/ |
| D | st33zp24-spi.txt | 1 * STMicroelectronics SAS. ST33ZP24 TPM SoC
4 - compatible: Should be "st,st33zp24-spi".
5 - spi-max-frequency: Maximum SPI frequency (<= 10000000).
8 - interrupts: GPIO interrupt to which the chip is connected
9 - lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 state.
12 Optional SoC Specific Properties:
13 - pinctrl-names: Contains only one value - "default".
14 - pintctrl-0: Specifies the pin control groups used for this controller.
16 Example (for ARM-based BeagleBoard xM with ST33ZP24 on SPI4):
23 compatible = "st,st33zp24-spi";
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| D | st33zp24-i2c.txt | 1 * STMicroelectronics SAS. ST33ZP24 TPM SoC
4 - compatible: Should be "st,st33zp24-i2c".
5 - clock-frequency: I²C work frequency.
6 - reg: address on the bus
9 - interrupts: GPIO interrupt to which the chip is connected
10 - lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 state.
13 Optional SoC Specific Properties:
14 - pinctrl-names: Contains only one value - "default".
15 - pintctrl-0: Specifies the pin control groups used for this controller.
17 Example (for ARM-based BeagleBoard xM with ST33ZP24 on I2C2):
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| /Documentation/devicetree/bindings/input/ |
| D | omap-keypad.txt | 3 TI's Keypad controller is used to interface a SoC with a matrix-type
6 The keypad controller can sense a key-press and key-release and report the
9 This binding is based on the matrix-keymap binding with the following
12 keypad,num-rows and keypad,num-columns are required.
14 Required SoC Specific Properties:
15 - compatible: should be one of the following
16 - "ti,omap4-keypad": For controllers compatible with omap4 keypad
20 - linux,keypad-no-autorepeat: do no enable autorepeat feature.
24 compatible = "ti,omap4-keypad";
25 keypad,num-rows = <2>;
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| D | twl4030-keypad.txt | 3 TWL4030's Keypad controller is used to interface a SoC with a matrix-type
6 The keypad controller can sense a key-press and key-release and report the
9 This binding is based on the matrix-keymap binding with the following
12 * keypad,num-rows and keypad,num-columns are required.
14 Required SoC Specific Properties:
15 - compatible: should be one of the following
16 - "ti,twl4030-keypad": For controllers compatible with twl4030 keypad
18 - interrupt: should be one of the following
19 - <1>: For controllers compatible with twl4030 keypad controller.
23 compatible = "ti,twl4030-keypad";
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| /Documentation/devicetree/bindings/net/ |
| D | apm-xgene-enet.txt | 1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
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| D | ftgmac100.txt | 4 - compatible: "faraday,ftgmac100"
7 or 2500 family SoC as they have some subtle tweaks to the
10 - "aspeed,ast2400-mac"
11 - "aspeed,ast2500-mac"
13 - reg: Address and length of the register set for the device
14 - interrupts: Should contain ethernet controller interrupt
17 - phy-mode: See ethernet.txt file in the same directory. If the property is
20 - use-ncsi: Use the NC-SI stack instead of an MDIO PHY. Currently assumes
21 rmii (100bT) but kept as a separate property in case NC-SI grows support
23 - no-hw-checksum: Used to disable HW checksum support. Here for backward
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| /Documentation/hwmon/ |
| D | scpi-hwmon.rst | 1 Kernel driver scpi-hwmon
6 * Chips based on ARM System Control Processor Interface
8 Addresses scanned: -
15 -----------
17 This driver supports hardware monitoring for SoC's based on the ARM
31 -----------
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