Searched full:translation (Results 1 – 25 of 150) sorted by relevance
123456
| /Documentation/translations/ |
| D | index.rst | 21 Translation's purpose is to ease reading and understanding in languages other
31 no guarantee that a translation is up to date. If what you read in a
32 translation does not sound right compared to what you read in the code, please
33 inform the translation maintainer and - if you can - check also the English
36 A translation is not a fork of the official documentation, therefore
41 accept only contributions that are merely translation related (e.g. new
46 grammar and culture, so the translation of an English statement may need to be
52 comfortable writing in English, you can ask the translation's maintainers
|
| /Documentation/scsi/ |
| D | aha152x.txt | 26 EXT_TRANS: enable extended translation (0/1: default 0 [off])
98 enable extended translation for first and second controller
133 This is considered to be the default translation.
138 extended translation. This means that the BIOS uses 255 for heads,
144 To make it even more complicated the translation mode might/might
150 - for disks<1GB: use default translation (C/32/64)
155 ie. either (C/32/64) or (C/63/255)). This can be extended translation
158 - if that fails, take extended translation if enabled by override,
159 kernel or module parameter, otherwise take default translation and
|
| /Documentation/devicetree/bindings/bus/ |
| D | uniphier-system-bus.txt | 8 controller registers provide the control for the translation from the offset
19 - ranges: should provide a proper address translation from the System Bus to
26 limitations depending on SoCs and the boot mode. The address translation is
33 There is no reason to stick to a particular translation mapping, but the
|
| /Documentation/virt/kvm/ |
| D | mmu.txt | 55 Translation
79 using kvm. Userspace defines the translation between guest addresses and user
98 - changes in the gpa->hpa translation (either through gpa->hva changes or
110 is not related to a translation directly. It points to other shadow pages.
114 translation stack, with optional higher level translations left to NPT/EPT.
128 (*) the guest hypervisor will encode the ngva->gpa translation into its page
137 Examples include real mode translation, large guest pages backed by small
219 translation. This is equivalent to the state of the tlb when a pte is
263 before using the translation. We take advantage of that by removing write
281 - a true guest fault (the guest translation won't allow the access) (*)
[all …]
|
| /Documentation/devicetree/bindings/iommu/ |
| D | samsung,sysmmu.txt | 7 System MMU is an IOMMU and supports identical translation table format to
8 ARMv7 translation tables with minimum set of page properties including access
10 another capabilities like L2 TLB or block-fetch buffers to minimize translation
|
| D | mediatek,iommu.txt | 6 ARM Short-Descriptor translation table format for address translation.
45 HW should go though the m4u for translation or bypass it and talk
|
| D | iommu.txt | 53 in order to enable translation for a given master. In such cases the single
80 be used for address translation. If a "dma-ranges" property exists in the
85 have a means to turn off translation. But it is invalid in such cases to
126 * Consequently address translation is always on or off for
|
| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | raideng.txt | 16 - ranges: standard ranges property specifying the translation
36 - ranges: standard ranges property specifying the translation
65 translation & protection accordingly.
|
| /Documentation/netlabel/ |
| D | lsm_interface.rst | 43 Depending on the exact configuration, translation between the network packet
52 NetLabel translation mechanisms bypassed but the LSM translation mechanisms are
|
| D | cipso_ipv4.rst | 41 Label Translation
51 Label Translation Cache
|
| /Documentation/arm64/ |
| D | tagged-pointers.rst | 10 addresses in the AArch64 translation system and their potential uses
13 The kernel configures the translation tables so that translations made
15 the virtual address ignored by the translation hardware. This frees up
|
| D | memory.rst | 8 Linux kernel. The architecture allows up to 4 levels of translation
11 AArch64 Linux uses either 3 levels or 4 levels of translation tables
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
19 number of descriptors in the first level of translation.
68 Translation table lookup with 4KB pages::
83 Translation table lookup with 64KB pages::
|
| /Documentation/translations/zh_CN/ |
| D | IRQ.txt | 6 help. Contact the Chinese maintainer if this translation is outdated
7 or if there is a problem with the translation.
|
| D | SecurityBugs | 6 help. Contact the Chinese maintainer if this translation is outdated
7 or if there is a problem with the translation.
|
| D | io_ordering.txt | 6 help. Contact the Chinese maintainer if this translation is outdated
7 or if there is a problem with the translation.
|
| D | sparse.txt | 6 help. Contact the Chinese maintainer if this translation is outdated
7 or if there is a problem with the translation.
|
| /Documentation/devicetree/bindings/pci/ |
| D | designware-pcie.txt | 24 - num-ib-windows: number of inbound address translation windows
25 - num-ob-windows: number of outbound address translation windows
40 Translation Unit) registers.
|
| /Documentation/input/ |
| D | notifier.rst | 17 - KBD_UNICODE events are sent if the keycode -> keysym translation produced a
19 - KBD_KEYSYM events are sent if the keycode -> keysym translation produced a
|
| /Documentation/translations/zh_CN/arm64/ |
| D | tagged-pointers.txt | 6 help. Contact the Chinese maintainer if this translation is outdated
7 or if there is a problem with the translation.
|
| D | legacy_instructions.txt | 6 help. Contact the Chinese maintainer if this translation is outdated
7 or if there is a problem with the translation.
|
| D | silicon-errata.txt | 6 help. Contact the Chinese maintainer if this translation is outdated
7 or if there is a problem with the translation.
|
| /Documentation/driver-api/ |
| D | ntb.rst | 8 registers and memory translation windows, as well as non common features like
42 inbound translation configured on the local ntb port and outbound translation
46 Inbound translation:
64 Outbound translation:
105 4) ntb_mw_set_trans(pidx, midx) - try to set translation address of
252 second half of the memory window for address translation to the peer.
|
| /Documentation/x86/x86_64/ |
| D | boot-options.rst | 310 Set the size of each PCI slot's translation table when using the
311 Calgary IOMMU. This is the size of the translation table itself
316 Enable translation even on slots that have no devices attached to
319 Disable translation on a given PHB. For
321 (PCI bus number 0); if translation (isolation) is enabled on this
|
| /Documentation/admin-guide/mm/ |
| D | concepts.rst | 51 translation from a virtual address used by programs to the physical
58 register. When the CPU performs the address translation, it uses this
69 The address translation requires several memory accesses and memory
71 processor cycles on the address translation, CPUs maintain a cache of
72 such translations called Translation Lookaside Buffer (or
|
| /Documentation/s390/ |
| D | vfio-ccw.rst | 25 (the real I/O subchannel device) to do further address translation and
105 vfio-ccw device does not have an IOMMU level translation or isolation.
109 policing and translation how the channel program is programmed before
240 * CCW translation APIs
241 A group of APIs (start with `cp_`) to do CCW translation. The CCWs
250 This driver utilizes the CCW translation APIs and introduces
262 channel program to the kernel, to do further CCW translation before
|
123456