Searched full:ultrascale (Results 1 – 10 of 10) sorted by relevance
| /Documentation/devicetree/bindings/clock/ |
| D | xlnx,zynqmp-clk.txt | 2 Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
5 The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
22 Input clocks for zynqmp Ultrascale+ clock controller:
24 The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
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| /Documentation/devicetree/bindings/reset/ |
| D | xlnx,zynqmp-reset.txt | 2 = Zynq UltraScale+ MPSoC reset driver binding =
4 The Zynq UltraScale+ MPSoC has several different resets.
6 See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
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| /Documentation/devicetree/bindings/fpga/ |
| D | xlnx,zynqmp-pcap-fpga.txt | 1 Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
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| /Documentation/devicetree/bindings/rtc/ |
| D | xlnx-rtc.txt | 1 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
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| /Documentation/devicetree/bindings/serial/ |
| D | cdns,uart.txt | 6 Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-zynqmp-qspi.txt | 1 Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
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| /Documentation/devicetree/bindings/nvmem/ |
| D | xlnx,zynqmp-nvmem.txt | 2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
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| /Documentation/devicetree/bindings/net/ |
| D | macb.txt | 17 Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
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| /Documentation/devicetree/bindings/arm/ |
| D | xilinx.yaml | 13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
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| /Documentation/devicetree/bindings/mailbox/ |
| D | xlnx,zynqmp-ipi-mailbox.txt | 5 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
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