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/Documentation/arm/
Dmemory.rst25 For SA11xx and Xscale, this is used to
38 fffe0000 fffeffff XScale cache flush area. This is used
39 in proc-xscale.S to flush the whole data
40 cache. (XScale does not have TCM.)
Dmarvel.rst322 * This line of SoCs originates from the XScale family developed by
327 * Due to their XScale origin, these SoCs have virtually nothing in
378 * This line of SoCs originates from the XScale family developed by
382 * Due to their XScale origin, these SoCs have virtually nothing in
429 The XScale cores were designed by Intel, and shipped by Marvell in the older
431 and that evolved into Sheeva. The XScale and Feroceon cores were phased out
435 XScale 1
438 XScale 2
441 XScale 3
/Documentation/devicetree/bindings/i2c/
Di2c-iop3xx.txt1 i2c Controller on XScale platforms such as IOP3xx and IXP4xx
/Documentation/devicetree/bindings/timer/
Dintel,ixp4xx-timer.yaml8 title: Intel IXP4xx XScale Networking Processors Timers
/Documentation/devicetree/bindings/gpio/
Dintel,ixp4xx-gpio.txt1 Intel IXP4xx XScale Networking Processors GPIO
/Documentation/devicetree/bindings/interrupt-controller/
Dintel,ixp4xx-interrupt.yaml8 title: Intel IXP4xx XScale Networking Processors Interrupt Controller
/Documentation/devicetree/bindings/misc/
Dintel,ixp4xx-ahb-queue-manager.yaml16 the XScale processor and the NPEs (Network Processing Units) in the
/Documentation/devicetree/bindings/serial/
D8250.txt24 - "intel,xscale-uart"
/Documentation/crypto/
Dasync-tx-api.txt38 present in the Intel(R) Xscale series of I/O processors. It also built
/Documentation/scsi/
DChangeLog.megaraid_sas205 a). reset the controller chips -- Xscale and Gen2 which
602 xscale controllers.