Searched full:xilinx (Results 1 – 25 of 50) sorted by relevance
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| /Documentation/devicetree/bindings/arm/ |
| D | xilinx.yaml | 4 $id: http://devicetree.org/schemas/arm/xilinx.yaml#
7 title: Xilinx Zynq Platforms Device Tree Bindings
10 - Michal Simek <michal.simek@xilinx.com>
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
49 - description: Xilinx internal board zc1232
55 - description: Xilinx internal board zc1254
61 - description: Xilinx internal board zc1275
67 - description: Xilinx 96boards compatible board zcu100
73 - description: Xilinx 96boards compatible board Ultra96
81 - description: Xilinx evaluation board zcu102
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| /Documentation/devicetree/bindings/ |
| D | xilinx.txt | 1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
4 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
232 That covers the general approach to binding xilinx IP cores into the
235 i) Xilinx ML300 Framebuffer
248 ii) Xilinx SystemACE
250 The Xilinx SystemACE device is used to program FPGAs from an FPGA
257 iii) Xilinx EMAC and Xilinx TEMAC
259 Xilinx Ethernet devices. In addition to general xilinx properties
264 iv) Xilinx Uartlite
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | video.txt | 1 DT bindings for Xilinx video IP cores
4 Xilinx video IP cores process video streams by acting as video sinks and/or
18 The following properties are common to all Xilinx video IP cores.
35 [UG934] http://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_vid…
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| D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP)
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
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| D | xlnx,v-tc.txt | 1 Xilinx Video Timing Controller (VTC)
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| /Documentation/devicetree/bindings/mailbox/ |
| D | xlnx,zynqmp-ipi-mailbox.txt | 1 Xilinx IPI Mailbox Controller
4 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
5 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
9 | Xilinx ZynqMP IPI Controller |
26 | Xilinx IPI Agent Block |
39 - xlnx,ipi-id: local Xilinx IPI agent ID
60 - xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
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| /Documentation/devicetree/bindings/fpga/ |
| D | xilinx-slave-serial.txt | 1 Xilinx Slave Serial SPI FPGA Manager
3 Xilinx Spartan-6 FPGAs support a method of loading the bitstream over
8 See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
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| D | xilinx-pr-decoupler.txt | 1 Xilinx LogiCORE Partial Reconfig Decoupler Softcore
3 The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
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| D | xilinx-zynq-fpga-mgr.txt | 1 Xilinx Zynq FPGA Manager
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| /Documentation/devicetree/bindings/rtc/ |
| D | xlnx-rtc.txt | 1 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
3 RTC controller for the Xilinx Zynq MPSoC Real Time Clock
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| /Documentation/driver-api/xilinx/ |
| D | eemi.rst | 2 Xilinx Zynq MPSoC EEMI Documentation
5 Xilinx Zynq MPSoC Firmware Interface
67 https://www.xilinx.com/support/documentation/user_guides/ug1200-eemi-api.pdf
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| D | index.rst | 3 Xilinx FPGA
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | xilinx-xadc.txt | 1 Xilinx XADC device driver
4 bindings are very similar. The Xilinx XADC is a ADC that can be found in the
5 series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication.
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| /Documentation/devicetree/bindings/dma/xilinx/ |
| D | xilinx_dma.txt | 1 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
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| D | zynqmp_dma.txt | 1 Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
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| /Documentation/devicetree/bindings/usb/ |
| D | udc-xilinx.txt | 1 Xilinx USB2 device controller
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| D | dwc3-xilinx.txt | 1 Xilinx SuperSpeed DWC3 USB SoC controller
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-xiic.txt | 1 Xilinx IIC controller:
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| /Documentation/devicetree/bindings/misc/ |
| D | xlnx,sd-fec.txt | 1 * Xilinx SDFEC(16nm) IP *
23 - reg: Should contain Xilinx SDFEC 16nm Hardened IP block registers
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-xilinx.txt | 1 Xilinx SPI controller Device Tree Bindings
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| /Documentation/devicetree/bindings/net/ |
| D | xilinx_axienet.txt | 1 XILINX AXI ETHERNET Device Tree Bindings
4 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
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| /Documentation/devicetree/bindings/sound/ |
| D | xlnx,i2s.txt | 1 Device-Tree bindings for Xilinx I2S PL block
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| D | xlnx,spdif.txt | 1 Device-Tree bindings for Xilinx SPDIF IP
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| D | xlnx,audio-formatter.txt | 1 Device-Tree bindings for Xilinx PL audio formatter
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| /Documentation/devicetree/bindings/serial/ |
| D | xlnx,opb-uartlite.txt | 1 Xilinx Axi Uartlite controller Device Tree Bindings
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