Searched full:zynq (Results 1 – 25 of 29) sorted by relevance
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| /Documentation/devicetree/bindings/arm/ |
| D | xilinx.yaml | 7 title: Xilinx Zynq Platforms Device Tree Bindings
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
23 - digilent,zynq-zybo
24 - digilent,zynq-zybo-z7
25 - xlnx,zynq-cc108
26 - xlnx,zynq-zc702
27 - xlnx,zynq-zc706
28 - xlnx,zynq-zc770-xm010
29 - xlnx,zynq-zc770-xm011
30 - xlnx,zynq-zc770-xm012
[all …]
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| /Documentation/devicetree/bindings/reset/ |
| D | zynq-reset.txt | 1 Xilinx Zynq Reset Manager
3 The Zynq AP-SoC has several different resets.
5 See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
8 - compatible: "xlnx,zynq-reset"
11 This should be a phandle to the Zynq's SLCR registers.
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
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| D | xlnx,zynqmp-reset.txt | 2 = Zynq UltraScale+ MPSoC reset driver binding =
4 The Zynq UltraScale+ MPSoC has several different resets.
6 See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
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| /Documentation/devicetree/bindings/net/can/ |
| D | xilinx_can.txt | 1 Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
19 - tx-fifo-depth : Can Tx fifo depth (Zynq, Axi CAN).
20 - rx-fifo-depth : Can Rx fifo depth (Zynq, Axi CAN, CAN FD in
29 For Zynq CANPS Dts file:
31 compatible = "xlnx,zynq-can-1.0";
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | synopsys.txt | 6 The Zynq DDR ECC controller has an optional ECC support in half-bus width
14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
23 compatible = "xlnx,zynq-ddrc-a05";
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| /Documentation/devicetree/bindings/fpga/ |
| D | xilinx-zynq-fpga-mgr.txt | 1 Xilinx Zynq FPGA Manager
4 - compatible: should contain "xlnx,zynq-devcfg-1.0"
13 compatible = "xlnx,zynq-devcfg-1.0";
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| D | xlnx,zynqmp-pcap-fpga.txt | 1 Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
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| /Documentation/devicetree/bindings/clock/ |
| D | zynq-7000.txt | 1 Device Tree Clock bindings for the Zynq 7000 EPP
3 The Zynq EPP has several different clk providers, each with there own bindings.
7 See Chapter 25 of Zynq TRM for more information about Zynq clocks.
10 The clock controller is a logical abstraction of Zynq's clock tree. It reads
19 (usually 33 MHz oscillators are used for Zynq platforms)
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| D | xlnx,zynqmp-clk.txt | 2 Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
3 Zynq MPSoC firmware interface
5 The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
24 The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | xilinx-xadc.txt | 7 available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The
14 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
20 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
76 compatible = "xlnx,zynq-xadc-1.00.a";
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-zynq-qspi.txt | 1 Xilinx Zynq QSPI controller Device Tree Bindings
5 - compatible : Should be "xlnx,zynq-qspi-1.0".
18 compatible = "xlnx,zynq-qspi-1.0";
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| D | spi-cadence.txt | 5 - compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
22 compatible = "xlnx,zynq-spi-r1p6";
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| D | spi-zynqmp-qspi.txt | 1 Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-zynq.txt | 1 Xilinx Zynq GPIO controller Device Tree Bindings
9 - compatible : Should be "xlnx,zynq-gpio-1.0" or "xlnx,zynqmp-gpio-1.0"
26 compatible = "xlnx,zynq-gpio-1.0";
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| /Documentation/devicetree/bindings/rtc/ |
| D | xlnx-rtc.txt | 1 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
3 RTC controller for the Xilinx Zynq MPSoC Real Time Clock
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | xlnx,zynq-pinctrl.txt | 1 Binding for Xilinx Zynq Pinctrl
4 - compatible: "xlnx,zynq-pinctrl"
12 Zynq's pin configuration nodes act as a container for an arbitrary number of
79 compatible = "xlnx,pinctrl-zynq";
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| /Documentation/devicetree/bindings/serial/ |
| D | cdns,uart.txt | 5 Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
6 Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
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| /Documentation/devicetree/bindings/net/ |
| D | macb.txt | 16 Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
17 Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
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| /Documentation/driver-api/xilinx/ |
| D | eemi.rst | 2 Xilinx Zynq MPSoC EEMI Documentation
5 Xilinx Zynq MPSoC Firmware Interface
19 EEMI ops is a structure containing all eemi APIs supported by Zynq MPSoC.
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| /Documentation/devicetree/bindings/power/ |
| D | xlnx,zynqmp-genpd.txt | 2 Device Tree Bindings for the Xilinx Zynq MPSoC PM domains
9 == Zynq MPSoC Generic PM Domain Node ==
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| /Documentation/devicetree/bindings/pci/ |
| D | xilinx-pcie.txt | 20 Optional properties for Zynq/Microblaze:
41 Zynq:
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| /Documentation/devicetree/bindings/watchdog/ |
| D | cadence-wdt.txt | 1 Zynq Watchdog Device Tree Bindings
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| /Documentation/devicetree/bindings/power/reset/ |
| D | xlnx,zynqmp-power.txt | 2 Device Tree Bindings for the Xilinx Zynq MPSoC Power Management
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| /Documentation/devicetree/bindings/soc/xilinx/ |
| D | xlnx,vcu.txt | 1 LogicoreIP designed compatible with Xilinx ZYNQ family.
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| /Documentation/devicetree/bindings/firmware/xilinx/ |
| D | xlnx,zynqmp-firmware.txt | 2 Device Tree Bindings for the Xilinx Zynq MPSoC Firmware Interface
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