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/Documentation/devicetree/bindings/watchdog/
Darm,sp805.txt14 2 clocks. With 2 clocks, the order is wdog_clk, apb_pclk
15 wdog_clk can be equal to or be a sub-multiple of the apb_pclk
17 - clock-names: Shall be "wdog_clk" for first clock and "apb_pclk" for the
30 clocks = <&wdt_clk>, <&apb_pclk>;
31 clock-names = "wdog_clk", "apb_pclk";
/Documentation/devicetree/bindings/pinctrl/
Daxis,artpec6-pinctrl.txt74 clocks = <&pll2div24>, <&apb_pclk>;
75 clock-names = "uart_clk", "apb_pclk";
83 clocks = <&pll2div24>, <&apb_pclk>;
84 clock-names = "uart_clk", "apb_pclk";
/Documentation/devicetree/bindings/arm/
Dcoresight.txt55 providing the interconnect should be "apb_pclk", and some
130 clock-names = "apb_pclk";
145 clock-names = "apb_pclk";
160 clock-names = "apb_pclk";
221 clock-names = "apb_pclk";
256 clock-names = "apb_pclk";
301 clock-names = "apb_pclk";
317 clock-names = "apb_pclk";
335 clock-names = "apb_pclk";
352 clock-names = "apb_pclk";
Dsp810.txt16 should be: "refclk", "timclk", "apb_pclk"
40 clock-names = "refclk", "timclk", "apb_pclk";
Dcoresight-cpu-debug.txt24 the interconnect should be "apb_pclk" and the clock is
47 clock-names = "apb_pclk";
Dprimecell.yaml34 const: apb_pclk
/Documentation/devicetree/bindings/crypto/
Drockchip-crypto.txt12 "apb_pclk" used to clock dma
25 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
/Documentation/devicetree/bindings/timer/
Darm,sp804.txt13 apb_pclk. A single clock can also be specified if the same clock is
28 clock-names = "timer1", "timer2", "apb_pclk";
/Documentation/devicetree/bindings/iio/adc/
Drockchip-saradc.txt16 - clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk" for
32 clock-names = "saradc", "apb_pclk";
/Documentation/devicetree/bindings/memory-controllers/
Dpl353-smc.txt10 - clock-names : List of input clock names - "memclk", "apb_pclk"
26 clock-names = "memclk", "apb_pclk";
Darm,pl172.txt21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
94 clock-names = "mpmcclk", "apb_pclk";
/Documentation/devicetree/bindings/serial/
Dsnps-dw-apb-uart.yaml57 - const: apb_pclk
134 clocks = <&baudclk>, <&apb_pclk>;
135 clock-names = "baudclk", "apb_pclk";
Dpl011.yaml70 - const: apb_pclk
123 clock-names = "uartclk", "apb_pclk";
/Documentation/devicetree/bindings/spi/
Dspi-rockchip.txt23 - clock-names: Shall be "spiclk" for the transfer-clock, and "apb_pclk" for
54 clock-names = "spiclk", "apb_pclk";
/Documentation/devicetree/bindings/dma/
Darm-pl08x.txt14 - clock-names: Must contain "apb_pclk"
44 clock-names = "apb_pclk";
Dlpc1850-dmamux.txt25 clock-names = "apb_pclk";
/Documentation/devicetree/bindings/thermal/
Drockchip-thermal.txt17 - clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for
42 clock-names = "tsadc", "apb_pclk";
/Documentation/devicetree/bindings/clock/
Dhix5hd2-clock.txt29 clock-names = "apb_pclk";
Dlsi,axm5516-clks.txt26 clock-names = "apb_pclk";
Dhi3670-clock.txt42 clock-names = "uartclk", "apb_pclk";
Dhi3660-clock.txt46 clock-names = "uartclk", "apb_pclk";
Drenesas,r9a06g032-sysctrl.txt44 clock-names = "baudclk", "apb_pclk";
/Documentation/devicetree/bindings/display/
Darm,pl11x.txt21 - clock-names: should contain "clcdclk" and "apb_pclk"
79 clock-names = "clcdclk", "apb_pclk";
/Documentation/devicetree/bindings/input/
Dti,nspire-keypad.txt35 clocks = <&apb_pclk>;
/Documentation/devicetree/bindings/mailbox/
Darm-mhu.txt36 clock-names = "apb_pclk";

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