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/Documentation/ABI/stable/
Dvdso1 On some architectures, when the kernel loads any userspace program it
23 ABI of those symbols is considered stable. It may vary across architectures,
27 The maintainers of the other vDSO-using architectures should confirm
/Documentation/virt/kvm/
Dapi.txt102 Architectures: which instruction set architectures provide this ioctl.
116 Architectures: all
132 Architectures: all
184 Architectures: x86
219 Architectures: all
237 Architectures: all
250 Architectures: all
261 Architectures: all
307 Architectures: all
339 Architectures: x86
[all …]
/Documentation/arm/
Dsetup.rst7 for most ARM Linux architectures.
61 based machines. May be used differently by different architectures.
65 different architectures.
69 architectures.
102 then a value of 50 Mhz is the default on 21285 architectures.
/Documentation/
Dunaligned-memory-access.txt13 Linux runs on a wide variety of architectures which have varying behaviour
46 In reality, only a few architectures require natural alignment on all sizes
47 of memory access. However, we must consider ALL supported architectures;
59 - Some architectures are able to perform unaligned memory accesses
61 - Some architectures raise processor exceptions when unaligned accesses
64 - Some architectures raise processor exceptions when unaligned accesses
67 - Some architectures are not capable of unaligned memory access, but will
246 On architectures that require aligned loads, networking requires that the IP
249 architectures this constant has the value 2 because the normal ethernet
258 unnecessary on architectures that can do unaligned accesses, the code can be
DIRQ.txt21 Architectures can assign additional meaning to the IRQ numbers, and
Datomic_t.txt152 are time critical and can, (typically) on LL/SC architectures, be more
201 These helper barriers exist because architectures have varying implicit
202 ordering on their SMP atomic primitives. For example our TSO architectures
/Documentation/media/kapi/
Dv4l2-clocks.rst14 this purpose. However, it is not (yet) available on all architectures. Besides,
31 architectures this API will be removed.
/Documentation/vm/
Dnuma.rst51 architectures. As with physical cells, software nodes may contain 0 or more
57 For some architectures, such as x86, Linux will "hide" any node representing a
60 these architectures, one cannot assume that all CPUs that Linux associates with
63 In addition, for some architectures, again x86 is an example, Linux supports
119 On architectures that do not hide memoryless nodes, Linux will include only
147 architectures transparently, kernel subsystems can use the numa_mem_id()
Dremap_file_pages.rst19 architectures. It would be nice to free up the flag for other usage.
Dmemory-model.rst24 although it is still in use by several architectures.
45 maps the entire physical memory. For most architectures, the holes
95 Architectures that support DISCONTIGMEM provide :c:func:`pfn_to_nid`
Dhighmem.rst29 The traditional split for architectures using this approach is 3:1, 3GiB for
45 Other architectures that have mm context tagged TLBs can have separate kernel
/Documentation/admin-guide/
Dcputopology.rst6 to /proc/cpuinfo output of some architectures. They reside in
113 To be consistent on all architectures, include/linux/topology.h
124 For architectures that don't support books (CONFIG_SCHED_BOOK) there are no
126 For architectures that don't support drawers (CONFIG_SCHED_DRAWER) there are
Dhighuid.rst15 What's left to be done for 32-bit UIDs on all Linux architectures:
23 architectures, this should not be a problem.
Defi-stub.rst14 between architectures is in drivers/firmware/efi/libstub.
86 For the ARM and arm64 architectures, a device tree must be provided to
/Documentation/features/
Darch-support.txt4 support matrix, for all upstream Linux architectures.
/Documentation/bpf/
Dbpf_design_QA.rst34 with two most used architectures x64 and arm64 (and takes into
35 consideration important quirks of other architectures) and
37 convention of the linux kernel on those architectures.
135 impossible to make generic and efficient across CPU architectures.
150 A: Because architectures like sparc have register windows and in general
151 there are enough subtle differences between architectures, so naive
172 CPU architectures and 32-bit HW accelerators. Can true 32-bit registers
179 programs for 32-bit architectures.
186 (a mov32 variant). This means that for architectures without zext hardware
/Documentation/virt/kvm/devices/
Dvcpu.txt11 Architectures: ARM64
41 Architectures: ARM,ARM64
Dvm.txt13 Architectures: s390
45 Architectures: s390
176 Architectures: s390
207 Architectures: s390
240 Architectures: s390
/Documentation/devicetree/bindings/regmap/
Dregmap.txt12 architectures that typically run big-endian operating systems
/Documentation/arm/omap/
Domap_pm.rst23 - allow drivers which are shared with other architectures (e.g.,
28 architectures.
77 omap_pm_set_max_dev_wakeup_lat(), etc. Other architectures which do
/Documentation/admin-guide/mm/
Dconcepts.rst25 address ranges. Besides, different CPU architectures, and even
44 size of each page is architecture specific. Some architectures allow
77 Many modern CPU architectures allow mapping of the memory pages
115 architectures define all zones, and requirements for DMA are different
/Documentation/ioctl/
Dioctl-decoding.rst7 Most architectures use this generic format, but check
/Documentation/process/
Dvolatile-considered-harmful.rst58 architectures. Those accessors are written to prevent unwanted
77 architectures where direct I/O memory access does work. Essentially,
/Documentation/driver-api/thermal/
Dx86_pkg_temperature_thermal.rst16 Intel® 64 and IA-32 Architectures Software Developer’s Manual (Jan, 2013):
/Documentation/timers/
Dtimekeeping.rst146 Some architectures may have a limited set of time sources and lack a nice
160 Delay timers (some architectures only)
180 This is available on some architectures like OpenRISC or ARM.

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