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/Documentation/devicetree/bindings/sound/
Dbrcm,cygnus-audio.txt13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
41 assigned-clock-rates = <1769470191>,
Dmt2701-afe-pcm.txt47 - assigned-clocks: list of input clocks and dividers for the audio system.
49 - assigned-clocks-parents: parent of input clocks of assigned clocks.
50 - assigned-clock-rates: list of clock frequencies of assigned clocks.
138 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
142 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
144 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
/Documentation/devicetree/bindings/display/msm/
Ddpu.txt38 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
39 - assigned-clock-rates: list of clock frequencies sorted in the same order as
40 the assigned-clocks property.
70 - assigned-clocks: list of clock specifiers for clocks needing rate assignment
71 - assigned-clock-rates: list of clock frequencies sorted in the same order as
72 the assigned-clocks property.
87 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
88 assigned-clock-rates = <300000000>;
116 assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
118 assigned-clock-rates = <0 0 300000000 19200000>;
/Documentation/devicetree/bindings/rtc/
Dst,stm32-rtc.txt25 - assigned-clocks: reference to the rtc_ck clock entry.
26 - assigned-clock-parents: phandle of the new parent clock of rtc_ck.
34 assigned-clocks = <&rcc 1 CLK_RTC>;
35 assigned-clock-parents = <&rcc 1 CLK_LSE>;
46 assigned-clocks = <&rcc RTC_CK>;
47 assigned-clock-parents = <&rcc LSE_CK>;
/Documentation/devicetree/bindings/spi/
Dspi-slave-mt27xx.txt13 - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
14 - assigned-clock-parents: parent of mux clock.
30 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
31 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
/Documentation/devicetree/bindings/ata/
Dqcom-sata.txt22 - assigned-clocks : Shall be:
25 - assigned-clock-rates : Shall be:
43 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
44 assigned-clock-rates = <100000000>, <100000000>;
/Documentation/devicetree/bindings/display/hisilicon/
Dhisi-ade.txt20 - assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
22 - assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
54 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
56 assigned-clock-rates = <360000000>, <288000000>;
/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
46 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
47 assigned-clock-rates = <50000000>;
70 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
71 assigned-clock-rates = <50000000>;
Dti,phy-am654-serdes.txt27 - assigned-clocks: As defined in
29 - assigned-clock-parents: As defined in
56 The assigned-clocks and assigned-clock-parents is used here to set the
70 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
71 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
/Documentation/devicetree/bindings/clock/
Dclock-bindings.txt135 ==Assigned clock parents and rates==
139 node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
140 properties. The assigned-clock-parents property should contain a list of parent
142 assigned-clock-rates property should contain a list of frequencies in Hz. Both
143 these properties should correspond to the clocks listed in the assigned-clocks
156 assigned-clocks = <&clkcon 0>, <&pll 2>;
157 assigned-clock-parents = <&pll 2>;
158 assigned-clock-rates = <0>, <460800>;
162 the <&pll 2> clock is assigned a frequency value of 460800 Hz.
Dcirrus,lochnagar.txt55 - assigned-clocks : A list of Lochnagar clocks to be reparented, see
57 - assigned-clock-parents : Parents to be assigned to the clocks
58 listed in "assigned-clocks".
83 assigned-clocks = <&lochnagar-clk LOCHNAGAR_CDC_MCLK1>,
85 assigned-clock-parents = <&clk-audio>,
/Documentation/devicetree/bindings/pwm/
Dpwm-sprd.txt16 - assigned-clocks: Reference to the PWM clock entries.
17 - assigned-clock-parents: The phandle of the parent clock of PWM clock.
31 assigned-clocks = <&aon_clk CLK_PWM0>,
35 assigned-clock-parents = <&ext_26m>,
/Documentation/devicetree/bindings/arm/
Dsp810.txt27 - assigned-clocks: from the common clock binding;
31 - assigned-clock-parents: from the common clock binding;
43 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
44 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…
/Documentation/ABI/testing/
Dsysfs-bus-pci-drivers-xhci_hcd13 When the DbC is enabled, the root port will be assigned
14 to the Debug Capability. Otherwise, it will be assigned
18 functionality and the shared root port will be assigned
Dsysfs-bus-typec30 With some alternate modes (SVIDs), the mode index is assigned
35 assigned, and can not be therefore used for identification. When
36 the mode index is not assigned, identifying the alternate mode
43 The Standard or Vendor ID (SVID) assigned by USB-IF for this
Dsysfs-devices-software_node6 assigned in kernel (i.e. software), as opposed to the
8 assigned for the device in firmware. The main attributes in the
Dsysfs-class-rapidio9 NOTE: An mport ID is not a RapidIO destination ID assigned to a
28 (RO) reports RapidIO destination ID assigned to the given
30 that no valid destination ID have been assigned to the mport
33 assigned to them using "hdid=..." rapidio module parameter.
/Documentation/devicetree/bindings/net/
Dmediatek-dwmac.txt44 - assigned-clocks: mac_main and ptp_ref clocks
45 - assigned-clock-parents: parent clocks of the assigned clocks
64 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
66 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
/Documentation/devicetree/bindings/mtd/
Dvf610-nfc.txt12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
47 assigned-clocks = <&clks VF610_CLK_NFC>;
48 assigned-clock-rates = <33000000>;
/Documentation/s390/
Dvfio-ap.rst10 The AP devices provide cryptographic functions to all CPUs assigned to a
27 functions. There can be from 0 to 256 adapters assigned to an LPAR. Adapters
28 assigned to the LPAR in which a linux host is running will be available to
34 The AP adapter cards are assigned to a given LPAR via the system's Activation
36 in the LPAR, the AP bus detects the AP adapter cards assigned to the LPAR and
37 creates a sysfs device for each assigned adapter. For example, if AP adapters
38 4 and 10 (0x0a) are assigned to the LPAR, the AP bus will create the following
68 The AP usage and control domains are assigned to a given LPAR via the system's
71 domains assigned to the LPAR. The domain number of each usage domain and
91 domains 6 and 71 (0x47) are assigned to the LPAR, the AP bus will create the
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/Documentation/devicetree/bindings/display/rockchip/
Dcdn-dp-rockchip.txt19 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
20 - assigned-clock-rates : the DP core clk frequency, shall be: 100000000
44 assigned-clocks = <&cru SCLK_DP_CORE>;
45 assigned-clock-rates = <100000000>;
/Documentation/devicetree/bindings/mmc/
Dsdhci-sprd.txt20 - assigned-clocks: the same with "sdio" clock
21 - assigned-clock-parents: the default parent of "sdio" clock
53 assigned-clocks = <&ap_clk CLK_EMMC_2X>;
54 assigned-clock-parents = <&rpll CLK_RPLL_390M>;
Dmtk-sd.txt36 - assigned-clocks: PLL of the source clock
37 - assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
66 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
67 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
/Documentation/devicetree/bindings/watchdog/
Dfsl-imx7ulp-wdt.txt19 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
20 assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
/Documentation/devicetree/bindings/media/
Dmediatek-vcodec.txt69 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
74 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
77 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
117 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
119 assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,

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