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/Documentation/driver-api/md/
Draid5-cache.rst7 caches data to the RAID disks. The cache can be in write-through (supported
8 since 4.4) or write-back mode (supported since 4.10). mdadm (supported since
9 3.4) has a new option '--write-journal' to create array with cache. Please
10 refer to mdadm manual for details. By default (RAID array starts), the cache is
11 in write-through mode. A user can switch it to write-back mode by::
13 echo "write-back" > /sys/block/md0/md/journal_mode
15 And switch it back to write-through mode by::
17 echo "write-through" > /sys/block/md0/md/journal_mode
19 In both modes, all writes to the array will hit cache disk first. This means
22 write-through mode
[all …]
/Documentation/scsi/
Dsd-parameters.txt5 ---------------
9 ----------------------------+---------+-------------+------------
12 write back | 1 0 | on | on
13 write back, no read (daft) | 1 1 | on | off
15 To set cache type to "write back" and save this setting to the drive:
17 # echo "write back" > cache_type
19 To modify the caching mode without making the change persistent, prepend
20 "temporary " to the cache type string. E.g.:
22 # echo "temporary write back" > cache_type
/Documentation/ABI/testing/
Dsysfs-class-bdi14 non-block filesystems which provide their own BDI, such as NFS
17 MAJOR:MINOR-fuseblk
23 The default backing dev, used for non-block device backed
27 ---------------------------------
29 read_ahead_kb (read-write)
31 Size of the read-ahead window in kilobytes
33 min_ratio (read-write)
36 total write-back cache that relates to its current average
37 writeout speed in relation to the other devices.
40 percentage of the write-back cache to a particular device.
[all …]
Dsysfs-platform-hidma-mgmt1 What: /sys/devices/platform/hidma-mgmt*/chanops/chan*/priority
10 What: /sys/devices/platform/hidma-mgmt*/chanops/chan*/weight
19 What: /sys/devices/platform/hidma-mgmt*/chreset_timeout_cycles
25 Contains the platform specific cycle value to wait after a
31 What: /sys/devices/platform/hidma-mgmt*/dma_channels
38 of HIDMA hardware. The value may change from chip to chip.
40 What: /sys/devices/platform/hidma-mgmt*/hw_version_major
48 What: /sys/devices/platform/hidma-mgmt*/hw_version_minor
56 What: /sys/devices/platform/hidma-mgmt*/max_rd_xactions
63 read transactions that can be issued back to back.
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/Documentation/driver-api/
Ddell_rbu.rst15 It does not cover the support needed from applications to enable the BIOS to
16 update itself with the image downloaded in to the memory.
25 Please go to http://support.dell.com register and you can find info on
28 Libsmbios can also be used to update BIOS on Dell systems go to
34 using the driver breaks the image in to packets of fixed sizes and the driver
36 maintains a link list of packets for reading them back.
40 The rbu driver needs to have an application (as mentioned above)which will
41 inform the BIOS to enable the update in the next system reboot.
57 copied to a single contiguous block of physical memory.
63 changed to packets during the driver load time by specifying the load
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/Documentation/devicetree/bindings/dma/
Dqcom_hidma_mgmt.txt14 instance can use like maximum read/write request and number of bytes to
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
23 fragmented to multiples of this amount. This parameter is used while
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
28 fragmented to multiples of this amount. This parameter is used while
31 - max-write-transactions: This value is how many times a write burst is
32 applied back to back while writing to the destination before yielding
[all …]
/Documentation/devicetree/bindings/arm/msm/
Dqcom,idle-state.txt3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
6 The idle states supported by the QCOM SoC are defined as -
13 Standby: Standby does a little more in addition to architectural clock gating.
15 clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
16 trigger to execute the SPM state machine. The SPM state machine waits for the
17 interrupt to trigger the core back in to active. This triggers the cache
18 hierarchy to enter standby states, when all cpus are idle. An interrupt brings
19 the SPM state machine out of its wait, the next step is to ensure that the
20 cache hierarchy is also out of standby, and then the cpu is allowed to resume
[all …]
/Documentation/cpu-freq/
Damd-powernow.txt5 there is a different cpu-freq driver for each generation.
8 so it is safe to try each driver in turn when in doubt as to
11 Note that the functionality to change frequency (and voltage)
13 to load on processors without this capability. The capability
16 The drivers use BIOS supplied tables to obtain frequency and
21 6th Generation: powernow-k6
23 7th Generation: powernow-k7: Athlon, Duron, Geode.
25 8th Generation: powernow-k8: Athlon, Athlon 64, Opteron, Sempron.
30 BIOS supplied data, for powernow-k7 and for powernow-k8, may be
33 The powernow-k8 driver will attempt to use ACPI if so configured,
[all …]
/Documentation/devicetree/bindings/sound/
Dfsl,asrc.txt5 output clock. The driver currently works as a Front End of DPCM with other Back
6 Ends Audio controller such as ESAI, SSI and SAI. It has three pairs to support
11 - compatible : Contains "fsl,imx35-asrc" or "fsl,imx53-asrc".
13 - reg : Offset and length of the register set for the device.
15 - interrupts : Contains the spdif interrupt.
17 - dmas : Generic dma devicetree binding as described in
20 - dma-names : Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc".
22 - clocks : Contains an entry for each entry in clock-names.
24 - clock-names : Contains the following entries
25 "mem" Peripheral access clock to access registers.
[all …]
/Documentation/powerpc/
Dtransactional_memory.rst5 POWER kernel support for this feature is currently limited to supporting
8 This file aims to sum up how it is supported by Linux and what behaviour you
17 instructions are presented to delimit transactions; transactions are
18 guaranteed to either complete atomically or roll back and undo any partial
49 transactional or non-transactional accesses within the system. In this
50 example, the transaction completes as though it were normal straight-line code
52 atomic move of money from the current account to the savings account has been
59 state will roll back to that at the 'tbegin', and control will continue from
60 'tbegin+4'. The branch to abort_handler will be taken this second time; the
69 - Conflicts with cache lines used by other processors
[all …]
Ddawr-power9.rst6 if it points to cache inhibited (CI) memory. Currently Linux has no way to
26 PPC_PTRACE_GETHWDBGINFO call. This results in GDB falling back to
29 h_set_mode(DAWR) and h_set_dabr() will now return an error to the
35 migration from POWER8 to POWER9, at the cost of silently losing the
49 host. The watchpoint will fail and GDB will fall back to software
53 and configure the hardware to use the DAWR. This will run at full
55 guest is migrated to a POWER9 host, the watchpoint will be lost on the
56 POWER9. Loads and stores to the watchpoint locations will not be
58 migrated back to the POWER8 host, it will start working again.
62 Kernels (since ~v5.2) have an option to force enable the DAWR via::
[all …]
/Documentation/admin-guide/
Dkernel-per-CPU-kthreads.rst2 Reducing OS jitter due to per-cpu kthreads
5 This document lists per-CPU kthreads in the Linux kernel and presents
6 options to control their OS jitter. Note that non-per-CPU kthreads are
7 not listed here. To reduce OS jitter from non-per-CPU kthreads, bind
8 them to a "housekeeping" CPU dedicated to such work.
13 - Documentation/IRQ-affinity.txt: Binding interrupts to sets of CPUs.
15 - Documentation/admin-guide/cgroup-v1: Using cgroups to bind tasks to sets of CPUs.
17 - man taskset: Using the taskset command to bind tasks to sets
20 - man sched_setaffinity: Using the sched_setaffinity() system
21 call to bind tasks to sets of CPUs.
[all …]
/Documentation/block/
Ddeadline-iosched.rst5 This little file attempts to document how the deadline io scheduler works.
7 of interest to power users.
10 -----------------------
11 Refer to Documentation/block/switching-sched.rst for information on
12 selecting an io scheduler on a per-device basis.
14 ------------------------------------------------------------------------------
17 -----------------------
19 The goal of the deadline io scheduler is to attempt to guarantee a start
27 -----------------------
29 Similar to read_expire mentioned above, but for writes.
[all …]
/Documentation/maintainer/
Drebasing-and-merging.rst1 .. SPDX-License-Identifier: GPL-2.0
8 Git source-code management system. Git is a powerful tool with a lot of
10 ways to use those features. This document looks in particular at the use
15 One thing to be aware of in general is that, unlike many other projects,
19 maintainers result from a desire to avoid merges, while others come from
27 referred to as rebasing since both are done with the ``git rebase``
30 - Changing the parent (starting) commit upon which a series of patches is
36 - Changing the history of a set of patches by fixing (or deleting) broken
37 commits, adding patches, adding tags to commit changelogs, or changing
39 type of operation will be referred to as "history modification"
[all …]
/Documentation/vm/
Dzswap.rst11 in the process of being swapped out and attempts to compress them into a
12 dynamically allocated RAM-based memory pool. zswap basically trades CPU cycles
13 for potentially reduced swap I/O.  This trade-off can also result in a
29 throttling by the hypervisor. This allows more work to get done with less
30 impact to the guest workload and guests sharing the I/O subsystem
32 drastically reducing life-shortening writes.
34 Zswap evicts pages from compressed cache on an LRU basis to the backing swap
39 the ``enabled`` attribute to 1 at boot time. ie: ``zswap.enabled=1``. Zswap
41 An example command to enable zswap at runtime, assuming sysfs is mounted
48 back into memory all of the pages stored in the compressed pool. The
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/Documentation/media/uapi/v4l/
Dvidioc-enumaudioout.rst1 .. Permission is granted to copy, distribute and/or modify this
4 .. Foundation, with no Invariant Sections, no Front-Cover Texts
5 .. and no Back-Cover Texts. A copy of the license is included at
6 .. Documentation/media/uapi/fdl-appendix.rst.
8 .. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections
19 VIDIOC_ENUMAUDOUT - Enumerate audio outputs
33 File descriptor returned by :ref:`open() <func-open>`.
36 Pointer to struct :c:type:`v4l2_audioout`.
42 To query the attributes of an audio output applications initialize the
45 ioctl with a pointer to this structure. Drivers fill the rest of the
[all …]
Dvidioc-g-modulator.rst1 .. Permission is granted to copy, distribute and/or modify this
4 .. Foundation, with no Invariant Sections, no Front-Cover Texts
5 .. and no Back-Cover Texts. A copy of the license is included at
6 .. Documentation/media/uapi/fdl-appendix.rst.
8 .. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections
19 VIDIOC_G_MODULATOR - VIDIOC_S_MODULATOR - Get or set modulator attributes
36 File descriptor returned by :ref:`open() <func-open>`.
39 Pointer to struct :c:type:`v4l2_modulator`.
45 To query the attributes of a modulator applications initialize the
48 :ref:`VIDIOC_G_MODULATOR <VIDIOC_G_MODULATOR>` ioctl with a pointer to this structure. Drivers
[all …]
/Documentation/devicetree/bindings/iommu/
Dti,omap-iommu.txt4 - compatible : Should be one of,
5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance
10 - reg : Address space for the configuration registers
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
14 also refer to the generic bindings document for more info
[all …]
/Documentation/admin-guide/device-mapper/
Dwritecache.rst6 doesn't cache reads because reads are supposed to be cached in page cache
14 1. type of the cache device - "p" or "s"
16 - p - persistent memory
17 - s - SSD
26 offset from the start of cache device in 512-byte sectors
46 applicable only to persistent memory - use the FUA flag
47 when writing data from persistent memory back to the
50 applicable only to persistent memory - don't use the FUA
51 flag when writing back data and send the FLUSH request
54 - some underlying devices perform better with fua, some
[all …]
Dera.rst2 dm-era
8 dm-era is a target that behaves similar to the linear target. In
11 maintains the current era as a monotonically increasing 32-bit
15 partially invalidating the contents of a cache to restore cache
16 coherency after rolling back a vendor snapshot.
36 ----------
38 Possibly move to a new era. You shouldn't assume the era has
43 ------------------
45 Create a clone of the metadata, to allow a userland process to read it.
48 ------------------
[all …]
/Documentation/device-mapper/
Ddm-bow.txt4 dm_bow is a device mapper driver that uses the free space on a device to back up
6 change, or rolled back by removing the dm_bow device and running a command line
9 dm_bow has three states, set by writing ‘1’ or ‘2’ to /sys/block/dm-?/bow/state.
10 It is only possible to go from state 0 (initial state) to state 1, and then from
11 state 1 to state 2.
13 State 0: dm_bow collects all trims to the device and assumes that these mark
16 FITRIM ioctl on the file system then switch to state 1. These trims are not
17 propagated to the underlying device.
19 State 1: All writes to the device cause the underlying data to be backed up to
23 that sector 0 is used to keep a log of the latest changes, both to indicate that
[all …]
/Documentation/x86/
Dmtrr.rst1 .. SPDX-License-Identifier: GPL-2.0
7 :Authors: - Richard Gooch <rgooch@atnf.csiro.au> - 3 Jun 1999
8 - Luis R. Rodriguez <mcgrof@do-not-panic.com> - April 9, 2015
16 arch_phys_wc_add() in combination with ioremap_wc() to make MTRR effective on
17 non-PAT systems while a no-op but equally effective on PAT enabled systems.
21 firmware may still have implemented access to MTRRs which would be controlled
24 the platform code would need uncachable access to some of its fan control
26 place other than mtrr_type_lookup() to ensure any OS specific mapping requests
31 For details refer to :doc:`pat`.
35 the Memory Type Range Registers (MTRRs) may be used to control
[all …]
/Documentation/media/uapi/rc/
Drc-tables.rst1 .. Permission is granted to copy, distribute and/or modify this
4 .. Foundation, with no Invariant Sections, no Front-Cover Texts
5 .. and no Back-Cover Texts. A copy of the license is included at
6 .. Documentation/media/uapi/fdl-appendix.rst.
8 .. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections
16 Unfortunately, for several years, there was no effort to create uniform
17 IR keycodes for different devices. This caused the same IR keyname to be
19 that the same IR keyname to be mapped completely different on different
20 IR's. Due to that, V4L2 API now specifies a standard for mapping Media
29 devices (CONFIG_INPUT_EVDEV) it is possible for applications to access
[all …]
/Documentation/w1/slaves/
Dw1_therm.rst14 -----------
37 Parasite powered devices are limited to one slave performing a
39 powered it would be possible to convert all the devices at the same
40 time and then go back to read individual sensors. That isn't
44 Writing a value between 9 and 12 to the sysfs w1_slave file will change the
46 SRAM, so it is reset when the sensor gets power-cycled.
48 To store the current precision configuration into EEPROM, the value 0
49 has to be written to the sysfs w1_slave file. Since the EEPROM has a limited
52 The module parameter strong_pullup can be set to 0 to disable the
53 strong pullup, 1 to enable autodetection or 2 to force strong pullup.
[all …]
/Documentation/devicetree/bindings/timer/
Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
19 to deliver its interrupts via SPIs.
[all …]

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