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/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
28 [irqN]----> [gpio-bank (n)]
[all …]
Dpinctrl-sirf.txt4 - compatible : "sirf,prima2-pinctrl"
5 - reg : Address range of the pinctrl registers
6 - interrupts : Interrupts used by every GPIO group
7 - gpio-controller : Indicates this device is a GPIO controller
8 - interrupt-controller : Marks the device node as an interrupt controller
10 - sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m
11 - sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m
13 Please refer to pinctrl-bindings.txt in this directory for details of the common
19 Required subnode-properties:
20 - sirf,pins : An array of strings. Each string contains the name of a group.
[all …]
Datmel,at91-pinctrl.txt10 Please refer to pinctrl-bindings.txt in this directory for details of the
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
23 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
24 configured in this periph mode. All the periph and bank need to be describe.
29 Each line will represent a pio bank
33 Bank: 3 (A, B and C)
41 For each peripheral/bank we will descibe in a u32 if a pin can be
45 From the datasheet Table 10-2.
[all …]
Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
[all …]
Dsamsung-pinctrl.txt6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
[all …]
Dnuvoton,npcm7xx-pinctrl.txt3 The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
9 - #address-cells : should be 1.
10 - #size-cells : should be 1.
11 - compatible : "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
12 - ranges : defines mapping ranges between pin controller node (parent)
13 to GPIO bank node (children).
15 === GPIO Bank Subnode ===
17 The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
19 Required GPIO Bank subnode-properties:
20 - reg : specifies physical base address and size of the GPIO
[all …]
Dallwinner,sunxi-pinctrl.txt4 each bank has 32 pins. Each pin has 7 multiplexing functions, with
6 the pins includes drive strength and pull-up.
9 - compatible: Should be one of the following (depending on your SoC):
10 "allwinner,sun4i-a10-pinctrl"
11 "allwinner,sun5i-a10s-pinctrl"
12 "allwinner,sun5i-a13-pinctrl"
13 "allwinner,sun6i-a31-pinctrl"
14 "allwinner,sun6i-a31s-pinctrl"
15 "allwinner,sun6i-a31-r-pinctrl"
16 "allwinner,sun7i-a20-pinctrl"
[all …]
Dpinctrl-mcp23s08.txt2 8-/16-bit I/O expander with serial interface (I2C/SPI)
5 - compatible : Should be
6 - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version
7 - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
8 - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or
9 - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
11 - "microchip,mcp23s08" for 8 GPIO SPI version
12 - "microchip,mcp23s17" for 16 GPIO SPI version
13 - "microchip,mcp23s18" for 16 GPIO SPI version
14 - "microchip,mcp23008" for 8 GPIO I2C version or
[all …]
Dactions,s700-pinctrl.txt7 - compatible: Should be "actions,s700-pinctrl"
8 - reg: Should contain the register base address and size of
10 - clocks: phandle of the clock feeding the pin controller
11 - gpio-controller: Marks the device node as a GPIO controller.
12 - gpio-ranges: Specifies the mapping between gpio controller and
13 pin-controller pins.
14 - #gpio-cells: Should be two. The first cell is the gpio pin number
16 - interrupt-controller: Marks the device node as an interrupt controller.
17 - #interrupt-cells: Specifies the number of cells needed to encode an
21 bindings/interrupt-controller/interrupts.txt
[all …]
Dactions,s900-pinctrl.txt7 - compatible: Should be "actions,s900-pinctrl"
8 - reg: Should contain the register base address and size of
10 - clocks: phandle of the clock feeding the pin controller
11 - gpio-controller: Marks the device node as a GPIO controller.
12 - gpio-ranges: Specifies the mapping between gpio controller and
13 pin-controller pins.
14 - #gpio-cells: Should be two. The first cell is the gpio pin number
16 - interrupt-controller: Marks the device node as an interrupt controller.
17 - #interrupt-cells: Specifies the number of cells needed to encode an
21 bindings/interrupt-controller/interrupts.txt
[all …]
Dmeson,pinctrl.txt4 - compatible: one of "amlogic,meson8-cbus-pinctrl"
5 "amlogic,meson8b-cbus-pinctrl"
6 "amlogic,meson8m2-cbus-pinctrl"
7 "amlogic,meson8-aobus-pinctrl"
8 "amlogic,meson8b-aobus-pinctrl"
9 "amlogic,meson8m2-aobus-pinctrl"
10 "amlogic,meson-gxbb-periphs-pinctrl"
11 "amlogic,meson-gxbb-aobus-pinctrl"
12 "amlogic,meson-gxl-periphs-pinctrl"
13 "amlogic,meson-gxl-aobus-pinctrl"
[all …]
/Documentation/devicetree/bindings/mtd/
Dmtd-physmap.txt1 CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
6 - compatible : should contain the specific model of mtd chip(s)
7 used, if known, followed by either "cfi-flash", "jedec-flash",
8 "mtd-ram" or "mtd-rom".
9 - reg : Address range(s) of the mtd chip(s)
11 non-identical chips can be described in one node.
12 - bank-width : Width (in bytes) of the bank. Equal to the
14 - device-width : (optional) Width of a single mtd chip. If
15 omitted, assumed to be equal to 'bank-width'.
16 - #address-cells, #size-cells : Must be present if the device has
[all …]
Dgpmc-nor.txt4 child nodes of the GPMC controller with a name of "nor".
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 - bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
12 16-bit devices and so must be either 1 or 2 bytes.
13 - compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
14 - gpmc,cs-on-ns: Chip-select assertion time
15 - gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
16 - gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
17 - gpmc,oe-on-ns: Output-enable assertion time
18 - gpmc,oe-off-ns: Output-enable de-assertion time
[all …]
/Documentation/hwmon/
Dw83795.rst10 Addresses scanned: I2C 0x2c - 0x2f
18 Addresses scanned: I2C 0x2c - 0x2f
23 - Wei Song (Nuvoton)
24 - Jean Delvare <jdelvare@suse.de>
28 -----------
35 - W83795G
38 Pin Name Register Sysfs attribute
75 41 FANCTL1 10h (bank 2) pwm1
76 43 FANCTL2 11h (bank 2) pwm2
77 45 FANCTL3 12h (bank 2) pwm3
[all …]
Dw83627hf.rst29 -----------------
39 -----------
47 Super I/O chip and a second i2c-only Winbond chip (often a W83782D),
55 The `w83627_HF_` uses pins 110-106 as VID0-VID4. The `w83627_THF_` uses the
66 [1] http://www.lm-sensors.org/browser/lm-sensors/trunk/doc/vid
69 -------------------
76 lm-sensors) before loading the driver:
80 isaset -y -f 0x2e 0x87
81 isaset -y -f 0x2e 0x87
85 isaset -y 0x2e 0x2f 0x07 0x0b
[all …]
/Documentation/devicetree/bindings/gpio/
Dgpio.txt5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
17 meaningful name. The only case where an array of GPIOs is accepted is when
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
44 recommended to use the two-cell approach.
[all …]
Dgpio-omap.txt4 - compatible:
5 - "ti,omap2-gpio" for OMAP2 controllers
6 - "ti,omap3-gpio" for OMAP3 controllers
7 - "ti,omap4-gpio" for OMAP4 controllers
8 - reg : Physical base address of the controller and length of memory mapped
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - #gpio-cells : Should be two.
12 - first cell is the pin number
13 - second cell is used to specify optional parameters (unused)
14 - interrupt-controller: Mark the device node as an interrupt controller.
[all …]
/Documentation/devicetree/bindings/leds/
Dleds-lm36274.txt1 * Texas Instruments LM36274 4-Channel LCD Backlight Driver w/Integrated Bias
3 The LM36274 is an integrated four-channel WLED driver and LCD bias supply.
5 up to 29V total output voltage. The 11-bit LED current is programmable via
9 Documentation/devicetree/bindings/mfd/ti-lmu.txt
12 Documentation/devicetree/bindings/regulator/lm363x-regulator.txt
15 - compatible:
16 "ti,lm36274-backlight"
17 - reg : 0
18 - #address-cells : 1
19 - #size-cells : 0
[all …]
/Documentation/devicetree/bindings/misc/
Dqcom,fastrpc.txt3 The FastRPC implements an IPC (Inter-Processor Communication)
9 - compatible:
14 - label
17 Definition: should specify the dsp domain name this fastrpc
20 - #address-cells
25 - #size-cells
33 - All Compute context banks MUST contain the following properties:
35 - compatible:
38 Definition: must be "qcom,fastrpc-compute-cb"
40 - reg
[all …]
/Documentation/devicetree/bindings/net/
Dgpmc-eth.txt4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
8 the GPMC controller with an "ethernet" name.
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28 - compatible: Compatible string property for the ethernet child device.
[all …]
/Documentation/devicetree/bindings/hwlock/
Dhwlock.txt15 - #hwlock-cells: Specifies the number of cells needed to represent a
22 property "hwlocks", and an optional "hwlock-names" property.
25 - hwlocks: List of phandle to a hwlock provider node and an
27 #hwlock-cells. The list can have just a single hwlock
32 - hwlock-names: List of hwlock name strings defined in the same order
33 as the hwlocks, with one name per hwlock. Consumers can
34 use the hwlock-names to match and get a specific hwlock.
39 The following example has a node requesting a hwlock in the bank defined by
52 the hwlock device node 'hwlock1' with #hwlock-cells value of 1, and another
53 hwlock within the hwlock device node 'hwlock2' with #hwlock-cells value of 2.
Domap-hwspinlock.txt5 - compatible: Should be one of the following,
6 "ti,omap4-hwspinlock" for
8 "ti,am654-hwspinlock" for
10 - reg: Contains the hwspinlock module register address space
12 - ti,hwmods: Name of the hwmod associated with the hwspinlock device
14 - #hwlock-cells: Should be 1. The OMAP hwspinlock users will use a
15 0-indexed relative hwlock number as the argument
17 within a hwspinlock bank.
26 compatible = "ti,omap4-hwspinlock";
29 #hwlock-cells = <1>;
[all …]
/Documentation/devicetree/bindings/powerpc/fsl/
Dlbc.txt4 - name : Should be localbus
5 - #address-cells : Should be either two or three. The first cell is the
8 - #size-cells : Either one or two, depending on how large each chipselect
10 - ranges : Each range corresponds to a single chipselect, and cover
15 compatible = "fsl,mpc8272-localbus",
16 "fsl,pq2-localbus";
17 #address-cells = <2>;
18 #size-cells = <1>;
26 compatible = "jedec-flash";
28 bank-width = <4>;
[all …]
/Documentation/devicetree/bindings/dma/
Dnvidia,tegra210-adma.txt7 - compatible: Should contain one of the following:
8 - "nvidia,tegra210-adma": for Tegra210
9 - "nvidia,tegra186-adma": for Tegra186 and Tegra194
10 - reg: Should contain DMA registers location and length. This should be
11 a single entry that includes all of the per-channel registers in one
12 contiguous bank.
13 - interrupts: Should contain all of the per-channel DMA interrupts in
15 - clocks: Must contain one entry for the ADMA module clock
17 - clock-names: Must contain the name "d_audio" for the corresponding
19 - #dma-cells : Must be 1. The first cell denotes the receive/transmit
[all …]
/Documentation/devicetree/bindings/memory-controllers/fsl/
Difc.txt4 - name : Should be ifc
5 - compatible : should contain "fsl,ifc". The version of the integrated
9 - #address-cells : Should be either two or three. The first cell is the
12 - #size-cells : Either one or two, depending on how large each chipselect
14 - reg : Offset and length of the register set for the device
15 - interrupts: IFC may have one or two interrupts. If two interrupt
21 - little-endian : If this property is absent, the big-endian mode will
24 - ranges : Each range corresponds to a single chipselect, and covers
28 cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
34 compatible = "fsl,ifc", "simple-bus";
[all …]

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