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/Documentation/devicetree/bindings/clock/
Dlpc1850-cgu.txt5 a base clock and itself is one of the inputs to the two Clock
13 corresponds to one of the base clocks for the LPC18xx.
25 Shall define the base and range of the address space
29 are the base clock numbers defined below.
35 Shall be an ordered list of numbers defining the base clock
41 Which base clocks that are available on the CGU depends on the
42 specific LPC part. Base clocks are numbered from 0 to 27.
45 0 BASE_SAFE_CLK Base safe clock (always on) for WWDT
46 1 BASE_USB0_CLK Base clock for USB0
47 2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,
[all …]
Dnspire-clock.txt7 "lsi,nspire-cx-clock" for the base clock in the CX model
8 "lsi,nspire-classic-clock" for the base clock in the older model
10 - reg: Physical base address of the controller and length of memory mapped
Dlpc1850-ccu.txt3 Each CGU base clock has several clock branches which can be turned on
16 Shall define the base and range of the address space
22 Shall contain a list of phandles for the base clocks routed
23 from the CGU to the specific CCU. See mapping of base clocks
26 Shall contain a list of names for the base clock routed
/Documentation/driver-api/
Dinfrastructure.rst10 Device Drivers Base
13 .. kernel-doc:: drivers/base/init.c
16 .. kernel-doc:: drivers/base/driver.c
19 .. kernel-doc:: drivers/base/core.c
22 .. kernel-doc:: drivers/base/syscore.c
25 .. kernel-doc:: drivers/base/class.c
28 .. kernel-doc:: drivers/base/node.c
31 .. kernel-doc:: drivers/base/firmware_loader/main.c
34 .. kernel-doc:: drivers/base/transport_class.c
37 .. kernel-doc:: drivers/base/dd.c
[all …]
/Documentation/i2c/busses/
Dscx200_acb.rst12 * base: up to 4 ints
13 Base addresses for the ACCESS.bus controllers on SCx200 and SC1100 devices
15 By default the driver uses two base addresses 0x820 and 0x840.
16 If you want only one base address, specify the second as 0 so as to
28 The SC1100 WRAP boards are known to use base addresses 0x810 and 0x820.
32 scx200_acb.base=0x810,0x820
37 options scx200_acb base=0x810,0x820
/Documentation/admin-guide/device-mapper/
Dsnapshot.rst105 lvcreate -L 1G -n base volumeGroup
106 lvcreate -L 100M --snapshot -n snap volumeGroup/base
112 volumeGroup-base-real: 0 2097152 linear 8:19 384
115 volumeGroup-base: 0 2097152 snapshot-origin 254:11
118 brw------- 1 root root 254, 11 29 ago 18:15 /dev/mapper/volumeGroup-base-real
121 brw------- 1 root root 254, 10 29 ago 18:14 /dev/mapper/volumeGroup-base
142 volumeGroup-base-real: 0 2097152 linear 8:19 384
143 volumeGroup-base-cow: 0 204800 linear 8:19 2097536
144 volumeGroup-base: 0 2097152 snapshot-merge 254:11 254:12 P 16
147 brw------- 1 root root 254, 11 29 ago 18:15 /dev/mapper/volumeGroup-base-real
[all …]
/Documentation/scsi/
Dg_NCR5380.txt30 base=xx[,...] the port or base address(es) (for port or memory mapped, resp.)
40 ncr_addr=xx the port or base address (for port or memory
49 modprobe g_NCR5380 irq=5 base=0x350 card=1
54 modprobe g_NCR5380 base=0x350 card=0
59 modprobe g_NCR5380 irq=255 base=0xc8000 card=1
65 modprobe g_NCR5380 irq=0,7 base=0x240,0x300 card=3,4
/Documentation/devicetree/bindings/interrupt-controller/
Dal,alpine-msix.txt8 - reg: physical base address and size of the registers
12 - al,msi-base-spi: SPI base of the MSI frame
23 al,msi-base-spi = <160>;
Dmarvell,orion-intc.txt7 - reg: base address(es) of interrupt registers starting with CAUSE register
13 - 0 maps to bit 0 of first base address,
14 - 1 maps to bit 1 of first base address,
15 - 32 maps to bit 0 of second base address, and so on.
30 - reg: base address of bridge interrupt registers starting with CAUSE register
Dmarvell,odmi-controller.txt23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
25 i.e marvell,spi-base = <128> will use SPI #96.
41 marvell,spi-base = <128>, <136>, <144>, <152>;
/Documentation/devicetree/bindings/display/panel/
Dvl050_8048nt_c01.txt5 - power-supply: as specified in the base binding
8 - backlight: as specified in the base binding
9 - enable-gpios: as specified in the base binding
Dauo,g104sn02.txt5 - power-supply: as specified in the base binding
8 - backlight: as specified in the base binding
9 - enable-gpios: as specified in the base binding
Dgiantplus,gpm940b0.txt5 - power-supply: as specified in the base binding
8 - backlight: as specified in the base binding
9 - enable-gpios: as specified in the base binding
Dauo,g101evn010.txt5 - power-supply: as specified in the base binding
8 - backlight: as specified in the base binding
9 - enable-gpios: as specified in the base binding
Dsharp,ls020b1dd01d.txt5 - power-supply: as specified in the base binding
8 - backlight: as specified in the base binding
9 - enable-gpios: as specified in the base binding
Dinnolux,g070y2-l01.txt5 - power-supply: as specified in the base binding
8 - backlight: as specified in the base binding
9 - enable-gpios: as specified in the base binding
Dlemaker,bl035-rgb-002.txt5 - power-supply: as specified in the base binding
8 - backlight: as specified in the base binding
9 - enable-gpios: as specified in the base binding
Dcdtech,s043wq26h-ct7.txt5 - power-supply: as specified in the base binding
8 - backlight: as specified in the base binding
9 - enable-gpios: as specified in the base binding
Dcdtech,s070wv95-ct16.txt5 - power-supply: as specified in the base binding
8 - backlight: as specified in the base binding
9 - enable-gpios: as specified in the base binding
/Documentation/devicetree/bindings/net/
Dhisilicon-hns-dsaf.txt13 - reg: specifies base physical address(es) and size of the device registers.
14 The first region is external interface control register base and size(optional,
17 The second region is SerDes base register and size(optional, only used when
20 The third region is the PPE register base and size.
21 The fourth region is dsa fabric base register and size. It is not required for
23 - reg-names: may be ppe-base and(or) dsaf-base. It is used to find the
64 reg-names = "ppe-base", "dsaf-base";
Ddavinci-mdio.txt9 - reg : physical base address and size of the davinci mdio
16 Note: "ti,hwmods" field is used to fetch the base address and irq
17 resources from TI, omap hwmod data base during device registration.
18 Future plan is to migrate hwmod data base contents into device tree
/Documentation/media/v4l-drivers/
Dradiotrack.rst56 The RadioTrack (base) ioport is configurable for 0x30c or 0x20c. Only one
129 Default: BASE <-- 0xc8 (current volume, no stereo detect,
132 Card Off: BASE <-- 0x00 (audio mute, no stereo detect,
135 Card On: BASE <-- 0x00 (see "Card Off", clears any unfinished business)
136 BASE <-- 0xc8 (see "Default")
138 Volume Down: BASE <-- 0x48 (volume down, no stereo detect,
141 BASE <-- 0xc8 (see "Default")
143 Volume Up: BASE <-- 0x88 (volume up, no stereo detect,
146 BASE <-- 0xc8 (see "Default")
148 Check Stereo: BASE <-- 0xd8 (current volume, stereo detect,
[all …]
/Documentation/driver-api/firmware/
Drequest_firmware.rst20 .. kernel-doc:: drivers/base/firmware_loader/main.c
25 .. kernel-doc:: drivers/base/firmware_loader/main.c
30 .. kernel-doc:: drivers/base/firmware_loader/main.c
35 .. kernel-doc:: drivers/base/firmware_loader/main.c
49 .. kernel-doc:: drivers/base/firmware_loader/main.c
63 .. kernel-doc:: drivers/base/firmware_loader/main.c
/Documentation/x86/
Dmtrr.rst73 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
74 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
78 # echo "base=0xf8000000 size=0x400000 type=write-combining" >! /proc/mtrr
82 # echo "base=0xf8000000 size=0x400000 type=write-combining" >| /proc/mtrr
87 reg00: base=0x00000000 ( 0MB), size= 128MB: write-back, count=1
88 reg01: base=0x08000000 ( 128MB), size= 64MB: write-back, count=1
89 reg02: base=0xf8000000 (3968MB), size= 4MB: write-combining, count=1
91 This is for video RAM at base address 0xf8000000 and size 4 megabytes. To
92 find out your base address, you need to look at the output of your X
99 move the framebuffer base address, so the only value you can trust is
[all …]
/Documentation/devicetree/bindings/pwm/
Dpwm-bcm2835.txt5 - reg: physical base address and length of the controller's registers
6 - clocks: This clock defines the base clock frequency of the PWM hardware
8 the base period.

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