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/Documentation/media/uapi/v4l/
Dpixfmt-srggb10-ipu3.rst25 sRGB / Bayer formats with 10 bits per sample with every 25 pixels packed
26 to 32 bytes leaving 6 most significant bits padding in the last byte.
41 - G\ :sub:`0001low`\ (bits 7--2)
43 B\ :sub:`0000high`\ (bits 1--0)
44 - B\ :sub:`0002low`\ (bits 7--4)
46 G\ :sub:`0001high`\ (bits 3--0)
47 - G\ :sub:`0003low`\ (bits 7--6)
49 B\ :sub:`0002high`\ (bits 5--0)
53 - G\ :sub:`0005low`\ (bits 7--2)
55 B\ :sub:`0004high`\ (bits 1--0)
[all …]
Dpixfmt-srggb14p.rst31 bits per colour. Every four consecutive samples are packed into seven
32 bytes. Each of the first four bytes contain the eight high order bits
34 significants bits of each pixel, in the same order.
68 - G\ :sub:`01low bits 1--0`\ (bits 7--6)
70 B\ :sub:`00low bits 5--0`\ (bits 5--0)
72 - R\ :sub:`02low bits 3--0`\ (bits 7--4)
74 G\ :sub:`01low bits 5--2`\ (bits 3--0)
76 - G\ :sub:`03low bits 5--0`\ (bits 7--2)
78 R\ :sub:`02low bits 5--4`\ (bits 1--0)
92 - R\ :sub:`01low bits 1--0`\ (bits 7--6)
[all …]
Dpixfmt-srggb10p.rst30 bits per sample. Every four consecutive samples are packed into 5
31 bytes. Each of the first 4 bytes contain the 8 high order bits
33 bits of each pixel, in the same order.
55 - G\ :sub:`03low`\ (bits 7--6) B\ :sub:`02low`\ (bits 5--4)
57 G\ :sub:`01low`\ (bits 3--2) B\ :sub:`00low`\ (bits 1--0)
63 - R\ :sub:`13low`\ (bits 7--6) G\ :sub:`12low`\ (bits 5--4)
65 R\ :sub:`11low`\ (bits 3--2) G\ :sub:`10low`\ (bits 1--0)
71 - G\ :sub:`23low`\ (bits 7--6) B\ :sub:`22low`\ (bits 5--4)
73 G\ :sub:`21low`\ (bits 3--2) B\ :sub:`20low`\ (bits 1--0)
79 - R\ :sub:`33low`\ (bits 7--6) G\ :sub:`32low`\ (bits 5--4)
[all …]
Dpixfmt-srggb12p.rst28 bits per colour. Every two consecutive samples are packed into three
29 bytes. Each of the first two bytes contain the 8 high order bits of
31 bits of each pixel, in the same order.
53 - G\ :sub:`01low`\ (bits 7--4)
55 B\ :sub:`00low`\ (bits 3--0)
58 - G\ :sub:`03low`\ (bits 7--4)
60 B\ :sub:`02low`\ (bits 3--0)
65 - R\ :sub:`11low`\ (bits 7--4)
67 G\ :sub:`10low`\ (bits 3--0)
70 - R\ :sub:`13low`\ (bits 3--2)
[all …]
Dpixfmt-cnf4.rst9 Depth sensor confidence information as a 4 bits per pixel packed array
20 Bits 0-3 of byte n refer to confidence value of depth pixel 2*n,
21 bits 4-7 to confidence value of depth pixel 2*n+1.
30 * - Y'\ :sub:`01[3:0]`\ (bits 7--4) Y'\ :sub:`00[3:0]`\ (bits 3--0)
31 - Y'\ :sub:`03[3:0]`\ (bits 7--4) Y'\ :sub:`02[3:0]`\ (bits 3--0)
Dpixfmt-y10p.rst22 This is a packed grey-scale image format with a depth of 10 bits per
24 the first 4 bytes contain the 8 high order bits of the pixels, and
25 the 5th byte contains the 2 least significants bits of each pixel,
45 - Y'\ :sub:`03[1:0]`\ (bits 7--6) Y'\ :sub:`02[1:0]`\ (bits 5--4)
46 Y'\ :sub:`01[1:0]`\ (bits 3--2) Y'\ :sub:`00[1:0]`\ (bits 1--0)
/Documentation/devicetree/bindings/leds/
Dleds-lp55xx.txt41 clock-mode = /bits/ 8 <2>;
44 led-cur = /bits/ 8 <0x2f>;
45 max-cur = /bits/ 8 <0x5f>;
50 led-cur = /bits/ 8 <0x2f>;
51 max-cur = /bits/ 8 <0x5f>;
55 led-cur = /bits/ 8 <0x2f>;
56 max-cur = /bits/ 8 <0x5f>;
75 clock-mode = /bits/ 8 <1>;
79 led-cur = /bits/ 8 <0x14>;
80 max-cur = /bits/ 8 <0x20>;
[all …]
/Documentation/media/uapi/rc/
Drc-protos.rst34 This IR protocol uses manchester encoding to encode 14 bits. There is a
40 .. flat-table:: rc5 bits scancode mapping
83 done to keep it compatible with plain rc-5 where there are two start bits.
90 .. flat-table:: rc-5-sz bits scancode mapping
93 * - rc-5-sz bits
132 This rc-5 extended to encoded 20 bits. The is a 3555 microseconds space
135 .. flat-table:: rc-5x-20 bits scancode mapping
138 * - rc-5-sz bits
187 The scancode is a 16 bits value, where the address is the lower 8 bits
188 and the command the higher 8 bits; this is reversed from IR order.
[all …]
/Documentation/devicetree/bindings/input/touchscreen/
Dad7879.txt18 This property has to be a '/bits/ 8' value
23 This property has to be a '/bits/ 8' value
28 This property has to be a '/bits/ 8' value
33 This property has to be a '/bits/ 8' value
36 This property has to be a '/bits/ 8' value
48 adi,first-conversion-delay = /bits/ 8 <3>;
49 adi,acquisition-time = /bits/ 8 <1>;
50 adi,median-filter-size = /bits/ 8 <2>;
51 adi,averaging = /bits/ 8 <1>;
52 adi,conversion-interval = /bits/ 8 <255>;
[all …]
/Documentation/devicetree/bindings/leds/backlight/
Dlp855x.txt25 dev-ctrl = /bits/ 8 <0x00>;
30 rom-addr = /bits/ 8 <0x14>;
31 rom-val = /bits/ 8 <0xcf>;
36 rom-addr = /bits/ 8 <0x15>;
37 rom-val = /bits/ 8 <0xc7>;
42 rom-addr = /bits/ 8 <0x19>;
43 rom-val = /bits/ 8 <0x0f>;
53 dev-ctrl = /bits/ 8 <0x85>;
54 init-brt = /bits/ 8 <0x10>;
64 dev-ctrl = /bits/ 8 <0x41>;
[all …]
/Documentation/devicetree/bindings/opp/
Dqcom-nvmem-cpufreq.txt148 opp-hz = /bits/ 64 <307200000>;
154 opp-hz = /bits/ 64 <384000000>;
160 opp-hz = /bits/ 64 <422400000>;
166 opp-hz = /bits/ 64 <460800000>;
172 opp-hz = /bits/ 64 <480000000>;
178 opp-hz = /bits/ 64 <537600000>;
184 opp-hz = /bits/ 64 <556800000>;
190 opp-hz = /bits/ 64 <614400000>;
196 opp-hz = /bits/ 64 <652800000>;
202 opp-hz = /bits/ 64 <691200000>;
[all …]
/Documentation/filesystems/ext4/
Dgroup_descr.rst38 checksum is the lower 16 bits of the checksum of the FS UUID, the group
56 - Lower 32-bits of location of block bitmap.
60 - Lower 32-bits of location of inode bitmap.
64 - Lower 32-bits of location of inode table.
68 - Lower 16-bits of free block count.
72 - Lower 16-bits of free inode count.
76 - Lower 16-bits of directory count.
84 - Lower 32-bits of location of snapshot exclusion bitmap.
88 - Lower 16-bits of the block bitmap checksum.
92 - Lower 16-bits of the inode bitmap checksum.
[all …]
Dinodes.rst47 - Lower 16-bits of Owner UID.
51 - Lower 32-bits of size in bytes.
63 value and this field contains the lower 32 bits of the attribute value's
79 - Lower 16-bits of GID.
93 - Lower 32-bits of “block” count. If the huge\_file feature flag is not
120 - Lower 32-bits of extended attribute block. ACLs are of course one of
126 - Upper 32-bits of file/directory size. In ext2/3 this field was named
144 - Upper 16-bits of the inode checksum.
148 - Extra change time bits. This provides sub-second precision. See Inode
153 - Extra modification time bits. This provides sub-second precision.
[all …]
/Documentation/EDID/
Dedid.S36 /* Provide defaults for the timing bits */
68 /* Serial number. 32 bits, little endian. */
82 Bits 6-1 Reserved, must be 0
84 1 pixel per clock, up to 8 bits per color, MSB aligned,
86 Bits 6-5 Video white and sync levels, relative to blank
111 Bits 4-3 Display type: 00=monochrome; 01=RGB colour;
120 /* Red and green least-significant bits
121 Bits 7-6 Red x value least-significant 2 bits
122 Bits 5-4 Red y value least-significant 2 bits
123 Bits 3-2 Green x value lst-significant 2 bits
[all …]
/Documentation/devicetree/bindings/ata/
Dahci-ceva.txt11 ceva,pN-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
19 ceva,pN-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
27 ceva,pN-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
35 ceva,pN-retry-params = /bits/ 16 <RIT RCT>;
49 ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
50 ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
51 ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
52 ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
54 ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
55 ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
[all …]
/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-mediatek.txt34 opp-hz = /bits/ 64 <598000000>;
39 opp-hz = /bits/ 64 <747500000>;
44 opp-hz = /bits/ 64 <1040000000>;
49 opp-hz = /bits/ 64 <1196000000>;
54 opp-hz = /bits/ 64 <1300000000>;
94 opp-hz = /bits/ 64 <507000000>;
99 opp-hz = /bits/ 64 <702000000>;
104 opp-hz = /bits/ 64 <1001000000>;
109 opp-hz = /bits/ 64 <1105000000>;
114 opp-hz = /bits/ 64 <1183000000>;
[all …]
Dti-cpufreq.txt27 2. Which eFuse bits indicate this OPP is available
55 * 0x2 and 0x4 have eFuse bits that indicate if they are available or not
67 opp-hz = /bits/ 64 <300000000>;
74 opp-hz = /bits/ 64 <275000000>;
81 opp-hz = /bits/ 64 <300000000>;
88 opp-hz = /bits/ 64 <500000000>;
94 opp-hz = /bits/ 64 <600000000>;
100 opp-hz = /bits/ 64 <600000000>;
106 opp-hz = /bits/ 64 <720000000>;
112 opp-hz = /bits/ 64 <720000000>;
[all …]
/Documentation/devicetree/bindings/net/
Dmicrel.txt10 bits that are currently supported:
12 KSZ8001: register 0x1e, bits 15..14
13 KSZ8041: register 0x1e, bits 15..14
14 KSZ8021: register 0x1f, bits 5..4
15 KSZ8031: register 0x1f, bits 5..4
16 KSZ8051: register 0x1f, bits 5..4
17 KSZ8081: register 0x1f, bits 5..4
18 KSZ8091: register 0x1f, bits 5..4
/Documentation/virt/kvm/devices/
Dxics.txt19 64 bits of state which can be read and written using the
24 * Unused, 16 bits
26 * Pending interrupt priority, 8 bits
29 * Pending IPI (inter-processor interrupt) priority, 8 bits
32 * Pending interrupt source number, 24 bits
35 * Current processor priority, 8 bits
39 Each source has 64 bits of state that can be read and written using
45 * Destination (server number), 32 bits
49 * Priority, 8 bits
/Documentation/leds/
Dleds-mlxcpld.rst29 - Bits [3:0]
33 - Bits [7:4]
37 - Bits [3:0]
41 - Bits [7:4]
45 - Bits [3:0]
49 - Bits [7:4]
78 - Bits [3:0]
82 - Bits [3:0]
86 - Bits [3:0]
90 - Bits [7:4]
[all …]
/Documentation/
Dcrc32.txt22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
26 Note that a CRC is computed over a string of *bits*, so you have
27 to decide on the endianness of the bits within each byte. To get
56 But also notice how the next_input_bit() bits we're shifting into
58 32 bits later. Thus, the first 32 cycles of this are pretty boring.
65 can be precomputed, and merging in the final 32 zero bits to make room
87 As long as next_input_bit is returning the bits in a sensible order, we don't
88 *have* to wait until the last possible moment to merge in additional bits.
89 We can do it 8 bits at a time rather than 1 bit at a time::
109 If the input is a multiple of 32 bits, you can even XOR in a 32-bit
[all …]
/Documentation/admin-guide/mm/
Dsoft-dirty.rst10 1. Clear soft-dirty bits from the task's PTEs.
17 3. Read soft-dirty bits from the PTEs.
30 soft-dirty bits clear, the #PF-s that occur after that are processed fast.
33 bits on the PTE.
36 there is still a scenario when we can lose soft dirty bits -- a task
39 including soft dirty bits. To notify user space application about such
/Documentation/devicetree/bindings/gpu/
Darm,mali-bifrost.yaml87 opp-hz = /bits/ 64 <533000000>;
91 opp-hz = /bits/ 64 <450000000>;
95 opp-hz = /bits/ 64 <400000000>;
99 opp-hz = /bits/ 64 <350000000>;
103 opp-hz = /bits/ 64 <266000000>;
107 opp-hz = /bits/ 64 <160000000>;
111 opp-hz = /bits/ 64 <100000000>;
/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-single.txt11 for pinctrl-single,pins and 2 for pinctrl-single,bits
13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
37 /* input, enabled pullup bits, disabled pullup bits, mask */
43 /* input, enabled pulldown bits, disabled pulldown bits, mask */
46 * Two bits to control input bias pullup and pulldown: User should use
49 * Three bits to control input bias enable, pullup and pulldown. User should
51 enable bit should be included in pullup or pulldown bits.
66 /* input, enable bits, disable bits, mask */
97 register offset and value pairs using pinctrl-single,pins. Only the bits
[all …]
/Documentation/driver-api/
Dedac.rst19 output 4 and 8 bits each (x4, x8). Grouping several of these in parallel
20 provides the number of bits that the memory controller expects:
21 typically 72 bits, in order to provide 64 bits + 8 bits of ECC data.
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
56 one 64 bits parallel access. Typically used with SDR, DDR, DDR2 and DDR3
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
64 bits with ECC), the data flows to the CPU using a 128 bits parallel
70 accessed. Common chip-select rows for single channel are 64 bits, for
71 dual channel 128 bits. It may not be visible by the memory controller,

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