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/Documentation/devicetree/bindings/mfd/
Dtwl-familly.txt17 it is considered as an interrupt controller cascaded to the SoC one.
34 interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */
Dtwl4030-audio.txt32 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
Dtwl4030-power.txt40 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
/Documentation/devicetree/bindings/interrupt-controller/
Dti,c64x+megamod-pic.txt35 may be cascaded into the core interrupt controller. The megamodule PIC
38 interrupt sources, individual megamodule interrupts may be cascaded to
39 the core interrupt controller. When an individual interrupt is cascaded,
Darm,versatile-fpga-irq.txt34 - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
Dnxp,lpc3220-mic.txt17 - interrupts: empty for MIC interrupt controller, cascaded MIC
Dinterrupts.txt64 interrupts = <31>; /* Cascaded to vic */
Darm,gic.yaml18 Secondary GICs are cascaded into the upward interrupt controller and do not
/Documentation/driver-api/gpio/
Ddriver.rst258 most often cascaded off a parent interrupt controller, and in some special
280 - CASCADED INTERRUPT CHIPS: this means that the GPIO chip has one common
309 Cascaded GPIO irqchips
312 Cascaded GPIO irqchips usually fall in one of three categories:
314 - CHAINED CASCADED GPIO IRQCHIPS: these are usually the type that is embedded on
416 is a typical example of a cascaded interrupt handler using gpio_irq_chip:
492 - DEPRECATED: gpiochip_irqchip_add(): adds a chained cascaded irqchip to a
498 - gpiochip_irqchip_add_nested(): adds a nested cascaded irqchip to a gpiochip,
499 as discussed above regarding different types of cascaded irqchips. The
500 cascaded irq has to be handled by a threaded interrupt handler.
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/Documentation/devicetree/bindings/gpio/
D8xxx_gpio.txt16 The GPIO module may serve as another interrupt controller (cascaded to
/Documentation/arm/
Dvlocks.rst96 vlocks can be cascaded in a voting hierarchy to permit better scaling
/Documentation/networking/dsa/
Ddsa.rst31 with the ability to configure and manage cascaded switches on top of each other
221 a collection of dsa_chip_data structure if multiples switches are cascaded,
263 when using a cascaded setup
/Documentation/devicetree/bindings/powerpc/fsl/
Dmpc5200.txt176 cascaded off of peripheral interrupt 0, which the driver interprets as a
/Documentation/powerpc/
Deeh-pci-error-recovery.rst324 (HBA) resets. These are cascaded into a chain of attempted
/Documentation/s390/
Dcds.rst125 cascaded 8259 programmable interrupt controllers (PICs), that allow for a