Searched full:cell (Results 1 – 25 of 519) sorted by relevance
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| /Documentation/devicetree/bindings/net/ |
| D | ibm,emac.txt | 24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
26 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
28 - cell-index : 1 cell, hardware index of the EMAC cell on a given
31 - max-frame-size : 1 cell, maximum frame size supported in bytes
32 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
35 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
38 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
41 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
48 - mdio-device : 1 cell, required iff using shared MDIO registers
51 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
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| D | fsl-fman.txt | 32 - cell-index
37 The cell-index value may be used by the SoC, to identify the
39 there's a description of the cell-index use in each SoC:
42 register[bit] FMan unit cell-index
47 register[bit] FMan unit cell-index
54 register[bit] FMan unit cell-index
101 channels in the FMan. The first cell specifies the beginning
102 of the range and the second cell specifies the number of
170 - cell-index
184 The page of a specific port is determined by the cell-index.
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| D | broadcom-bcm87xx.txt | 9 - broadcom,c45-reg-init : one of more sets of 4 cells. The first cell
11 address within the MMD, the third cell contains a mask to be ANDed
12 with the existing register value, and the fourth cell is ORed with
13 he result to yield the new register value. If the third cell has a
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | bootbus.txt | 13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
29 - cavium,cs-index: A single cell indicating the chip select that
32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
36 - cavium,t-oe: A cell specifying the OE timing (in nS).
38 - cavium,t-we: A cell specifying the WE timing (in nS).
40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
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| /Documentation/devicetree/bindings/powerpc/4xx/ |
| D | cpm.txt | 16 - unused-units : specifier consist of one cell. For each
17 bit in the cell, the corresponding bit
20 - idle-doze : specifier consist of one cell. For each
21 bit in the cell, the corresponding bit
24 - standby : specifier consist of one cell. For each
25 bit in the cell, the corresponding bit
28 - suspend : specifier consist of one cell. For each
29 bit in the cell, the corresponding bit
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | cdns,xtensa-pic.txt | 8 When it's 1, the first cell is the internal IRQ number.
9 When it's 2, the first cell is the IRQ number, and the second cell
19 /* one cell: internal irq number,
20 * two cells: second cell == 0: internal irq number
21 * second cell == 1: external irq number
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| D | cdns,xtensa-mx.txt | 12 /* one cell: internal irq number,
13 * two cells: second cell == 0: internal irq number
14 * second cell == 1: external irq number
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic.txt | 85 <1st-cell> interrupt-number
90 Note: If the interrupt-type cell is undefined
91 (i.e. #interrupt-cells = 2), this cell
96 <2nd-cell> level-sense information, encoded as follows:
102 <3rd-cell> interrupt-type
108 The interrupt-number cell contains
110 type-specific cell is undefined. The
121 The interrupt-number cell contains
124 cell identifies the specific error
129 The interrupt-number cell identifies
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| D | dma.txt | 14 - cell-index : controller index. 0 for controller @ 0x8100
21 - cell-index : DMA channel index starts at 0.
37 cell-index = <0>;
40 cell-index = <0>;
47 cell-index = <1>;
54 cell-index = <2>;
61 cell-index = <3>;
78 - cell-index : controller index. 0 for controller @ 0x21000,
86 - cell-index : DMA channel index starts at 0.
97 cell-index = <0>;
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | stm32-rproc.txt | 13 1st cell: phandle of syscon block
14 2nd cell: register offset containing the hold boot setting
15 3rd cell: register bitmask for the hold boot field
18 1st cell: phandle to syscon block
19 2nd cell: register offset containing the RCC trust zone mode setting
20 3rd cell: register bitmask for the RCC trust zone mode bit
48 1st cell: phandle to syscon block
49 2nd cell: register offset containing the deep sleep setting
50 3rd cell: register bitmask for the deep sleep bit
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio_atmel.txt | 7 - #gpio-cells: Should be two. The first cell is the pin number and
8 the second cell is used to specify optional parameters to declare if the GPIO
12 - #interrupt-cells: Should be two. The first cell is the pin number and the
13 second cell is used to specify irq type flags, see the two cell description
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| D | gpio-thunderx.txt | 7 - First cell is the GPIO pin number relative to the controller.
8 - Second cell is a standard generic flag bitfield as described in gpio.txt.
15 - First cell is the GPIO pin number relative to the controller.
16 - Second cell is triggering flags as defined in interrupts.txt.
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| D | gpio-twl4030.txt | 7 - first cell is the pin number
8 - second cell is used to specify optional parameters (unused)
12 The first cell is the GPIO number.
13 The second cell is not used.
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| D | fsl-imx-gpio.txt | 10 - #gpio-cells : Should be two. The first cell is the pin number and
11 the second cell is used to specify the gpio polarity:
15 - #interrupt-cells : Should be 2. The first cell is the GPIO number.
16 The second cell bits[3:0] is used to specify trigger type and level flags:
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| D | cdns,gpio.txt | 7 * first cell is the GPIO number.
8 * second cell specifies the GPIO flags, as defined in
22 * first cell is the GPIO number you want to use as an IRQ source.
23 * second cell specifies the IRQ type, as defined in
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| D | nvidia,tegra20-gpio.txt | 9 - #gpio-cells : Should be two. The first cell is the pin number and the
10 second cell is used to specify optional parameters:
14 The first cell is the GPIO number.
15 The second cell is used to specify flags:
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| D | gpio-zynq.txt | 6 - First cell is the GPIO line number
7 - Second cell is used to specify optional
15 - #interrupt-cells : Should be 2. The first cell is the GPIO number.
16 The second cell bits[3:0] is used to specify trigger type and level flags:
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| D | microchip,pic32-gpio.txt | 8 - #gpio-cells: Two. The first cell is the pin number and
9 the second cell is used to specify the gpio polarity as defined in
15 - #interrupt-cells: Two. The first cell is the GPIO number and second cell
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| /Documentation/devicetree/bindings/clock/ |
| D | ux500.txt | 13 - prcmu-clock: a subnode with one clock cell for PRCMU (power,
14 reset, control unit) clocks. The cell indicates which PRCMU
18 The first cell indicates which PRCC block the consumer
20 cell indicates which clock inside the PRCC block it wants,
24 The first cell indicates which PRCC block the consumer
26 cell indicates which clock inside the PRCC block it wants,
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| /Documentation/driver-api/ |
| D | nvmem.rst | 85 Additionally it is possible to create nvmem cell lookup entries and register
103 3. NVMEM cell based consumer APIs
112 void nvmem_cell_put(struct nvmem_cell *cell);
113 void devm_nvmem_cell_put(struct device *dev, struct nvmem_cell *cell);
115 void *nvmem_cell_read(struct nvmem_cell *cell, ssize_t *len);
116 int nvmem_cell_write(struct nvmem_cell *cell, void *buf, ssize_t len);
118 `*nvmem_cell_get()` apis will get a reference to nvmem cell for a given id,
119 and nvmem_cell_read/write() can then read or write to the cell.
120 Once the usage of the cell is finished the consumer should call
121 `*nvmem_cell_put()` to free all the allocation memory for the cell.
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| /Documentation/media/uapi/v4l/ |
| D | ext-ctrls-detect.rst | 44 - The image is divided into a grid, each cell with its own motion
48 - The image is divided into a grid, each cell with its own region
62 Sets the motion detection thresholds for each cell in the grid. To
64 detection mode. Matrix element (0, 0) represents the cell at the
68 Sets the motion detection region value for each cell in the grid. To
70 detection mode. Matrix element (0, 0) represents the cell at the
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| /Documentation/devicetree/bindings/ |
| D | jailhouse.txt | 1 Jailhouse non-root cell device tree bindings
4 When running in a non-root Jailhouse cell (partition), the device tree of this
8 - compatible = "jailhouse,cell"
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| /Documentation/devicetree/bindings/reset/ |
| D | ti-syscon-reset.txt | 33 Cell #1 : offset of the reset assert control
35 Cell #2 : bit position of the reset in the reset
37 Cell #3 : offset of the reset deassert control
39 Cell #4 : bit position of the reset in the reset
41 Cell #5 : offset of the reset status register
43 Cell #6 : bit position of the reset in the
45 Cell #7 : Flags used to control reset behavior,
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| /Documentation/filesystems/ |
| D | afs.txt | 12 - The cell database.
65 When inserting the driver modules the root cell must be specified along with a
84 Where the parameters to the "add" command are the name of a cell and a list of
85 volume location servers within that cell, with the latter separated by colons.
90 mount -t afs "#cambridge.redhat.com:root.cell." /afs/cambridge
92 mount -t afs "#root.cell." /afs/cambridge
101 The name of the cell is optional, and if not given during a mount, then the
102 named volume will be looked up in the cell specified during modprobe.
142 looks up a cell of the same name, for example:
160 (*) A directory per cell that contains files that list volume location
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| /Documentation/devicetree/bindings/mmc/ |
| D | fsl-imx-esdhc.txt | 32 required, first cell specifies minimum slot voltage (mV), second cell
34 - fsl,tuning-start-tap: Specify the start dealy cell point when send first CMD19
36 - fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure.
37 The uSDHC use one delay cell as default increasing step to do tuning process.
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