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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | resistive-adc-touch.txt | 6 The device must be connected to an ADC device that provides channels for
9 - iio-channels: must have at least two channels connected to an ADC device.
10 These should correspond to the channels exposed by the ADC device and should
11 have the right index as the ADC device registers them. These channels
13 - iio-channel-names: must have all the channels' names. Mandatory channels
17 - iio-channels: The third channel named "pressure" is optional and can be
28 io-channels = <&adc 24>, <&adc 25>, <&adc 26>;
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-sprd-adi.txt | 8 ADI controller has 50 channels including 2 software read/write channels and
9 48 hardware channels to access analog chip. For 2 software read/write channels,
10 users should set ADI registers to access analog chip. For hardware channels,
14 triggered by hardware components instead of ADI software channels.
16 Thus we introduce one property named "sprd,hw-channels" to configure hardware
17 channels, the first value specifies the hardware channel id which is used to
22 one system is reading/writing data by ADI software channels, that should be under
24 data by ADI software channels at the same time, or two parallel routine of setting
28 The new version ADI controller supplies multiple master channels for different
45 - sprd,hw-channels: This is an array of channel values up to 49 channels.
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| /Documentation/mips/ |
| D | ingenic-tcu.rst | 8 hardware block. It features up to to eight channels, that can be used as
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
12 have eight channels.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
28 - mode TCU1: channels cannot work in sleep mode, but are easier to
30 - mode TCU2: channels can work in sleep mode, but the operation is a bit
31 more complicated than with TCU1 channels.
35 - On the oldest SoCs (up to JZ4740), all of the eight channels operate in
38 - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
41 - Each channel can generate an interrupt. Some channels share an interrupt
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| /Documentation/ABI/stable/ |
| D | sysfs-bus-vmbus | 26 Description: The mapping of which primary/sub channels are bound to which
52 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>
59 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>/cpu
66 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>/cpu
73 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>/in_mask
80 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>/latency
85 performance critical channels (storage, network, etc.) that use
89 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>/out_mask
96 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>/pending
101 performance critical channels (storage, network, etc.) that use
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| /Documentation/devicetree/bindings/sound/ |
| D | rockchip-i2s.txt | 29 - rockchip,playback-channels: max playback channels, if not set, 8 channels default.
30 - rockchip,capture-channels: max capture channels, if not set, 2 channels default.
32 Required properties for controller which support multi channels
47 rockchip,playback-channels = <8>;
48 rockchip,capture-channels = <2>;
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| D | xlnx,i2s.txt | 12 - xlnx,num-channels: Number of I2S streams. Can be any of 1, 2, 3, 4.
13 supported channels = 2 * xlnx,num-channels
21 xlnx,num-channels = <1>;
27 xlnx,num-channels = <1>;
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | st,stm32-adc.txt | 4 It has several multiplexed input channels. Conversions can be performed
72 - st,adc-channels: List of single-ended channels muxed for this ADC.
73 It can have up to 16 channels on stm32f4 or 20 channels on stm32h7, numbered
75 - st,adc-diff-channels: List of differential channels muxed for this ADC.
76 Depending on part used, some channels can be configured as differential
80 Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is required.
81 Both properties can be used together. Some channels can be used as
82 single-ended and some other ones as differential (mixed). But channels
99 This can be either one value or an array that matches 'st,adc-channels' list,
100 to set sample time resp. for all channels, or independently for each channel.
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| D | adc.txt | 5 - diff-channels : Differential channels muxed for this ADC. The first value
15 diff-channels = <0 1>;
20 diff-channels = <2 3>;
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| D | cc10001_adc.txt | 11 - adc-reserved-channels: Bitmask of reserved channels,
12 i.e. channels that cannot be used by the OS.
18 adc-reserved-channels = <0x2>;
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| D | adi,ad7124.yaml | 69 Represents the external channels which are connected to the ADC.
75 The channel number. It can have up to 8 channels on ad7124-4
76 and 16 channels on ad7124-8, numbered from 0 to 15.
93 diff-channels:
113 - diff-channels
136 diff-channels = <0 1>;
144 diff-channels = <2 3>;
152 diff-channels = <4 5>;
157 diff-channels = <6 7>;
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| /Documentation/devicetree/bindings/dma/ |
| D | brcm,bcm2835-dma.txt | 3 The BCM2835 DMA controller has 16 channels in total.
4 Only the lower 13 channels have an associated IRQ.
5 Some arbitrary channels are used by the firmware
7 The channels 0,2 and 3 have special functionality
14 to the DMA channels in ascending order.
18 that is shared by all dma channels.
21 - brcm,dma-channel-mask: Bit mask representing the channels
46 /* unused shared irq for all channels */
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| D | snps,dw-axi-dmac.txt | 8 - dma-channels: Number of channels supported by hardware.
13 dma-channels. Priority value must be programmed within [0:dma-channels-1]
16 Array size is equal to the number of dma-channels.
33 dma-channels = <4>;
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| D | jz4780-dma.txt | 19 - ingenic,reserved-channels: Bitmask of channels to reserve for devices that
20 need a specific channel. These channels will only be assigned when explicitly
21 requested by a client. The primary use for this is channels 0 and 1, which
39 ingenic,reserved-channels = <0x3>;
50 should be reserved on the DMA controller using the ingenic,reserved-channels
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| D | ste-coh901318.txt | 10 - #dma-cells: must be set to <1>, as the channels on the
12 - dma-channels: the number of DMA channels handled
22 dma-channels = <40>;
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| D | ste-dma40.txt | 9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
26 memcpy-channels = <56 57 58 59 60>;
27 disabled-channels = <12>;
28 dma-channels = <8>;
34 - dma-names: Names of the aforementioned requested channels
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| D | renesas,rcar-dmac.txt | 4 controller instances named DMAC capable of serving multiple clients. Channels
10 256 clients in total. When the number of hardware channels is lower than the
11 number of clients to be served, channels must be shared between multiple DMA
12 clients. The association of DMA clients to DMAC channels is fully dynamic and
44 zero to the number of channels minus one.
53 - dma-channels: number of DMA channels
84 dma-channels = <15>;
114 dma-channels = <15>;
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| D | mmp-dma.txt | 13 - #dma-channels: Number of DMA channels supported by the controller (defaults
36 #dma-channels = <16>;
40 * One irq for all channels
48 #dma-channels = <16>;
74 /* One irq for all channels */
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| D | zxdma.txt | 8 - dma-channels: physical channels supported
9 - dma-requests: virtual channels supported, each virtual channel
22 dma-channels = <24>;
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| /Documentation/devicetree/bindings/iio/multiplexer/ |
| D | io-channel-mux.txt | 8 - io-channels : Channel node of the parent channel that has multiplexed
14 - channels : List of strings, labeling the mux controller states.
16 For each non-empty string in the channels property, an io-channel will
18 the list of strings in the channels property, and also matches the mux
33 io-channels = <&adc 0>;
38 channels = "sync", "in", "system-regulator";
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| /Documentation/trace/ |
| D | stm.rst | 11 these masters and channels are statically allocated to certain
24 48 to 63 and channels 0 to 127.
28 identifiers to ranges of masters and channels. If these rules (policy)
33 have a name (string identifier) and a range of masters and channels
41 channels masters
44 $ cat /config/stp-policy/dummy_stm.my-policy/user/channels
48 masters 48 through 63 and channel allocation pool has channels 0
78 contiguous range of master/channels from the beginning of the device's
85 mmu) will usually contain multiple channels' mmios, so the user will
86 need to allocate that many channels to themselves (via the
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| /Documentation/devicetree/bindings/timer/ |
| D | renesas,tmu.txt | 6 Channels share hardware resources but their counter and compare match value
7 are independent. The TMU hardware supports up to three channels.
31 - #renesas,channels: number of channels implemented by the timer, must be 2
46 #renesas,channels = <3>;
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| D | nvidia,tegra30-timer.txt | 3 The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
4 running counter, and 5 watchdog modules. The first two channels may also
13 - interrupts : A list of 6 interrupts; one per each of timer channels 1
14 through 5, and one for the shared interrupt for the remaining channels.
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| /Documentation/driver-api/dmaengine/ |
| D | dmatest.rst | 10 The test suite works only on the channels that have at least one
64 After the channels are specified, each thread is set as pending. All threads
68 A list of available channels can be found by running the following command::
143 Allocating Channels
146 Channels are required to be configured prior to starting the test run.
147 Attempting to run the test without configuring the channels will fail.
152 dmatest: Could not start test, no channels configured
154 Channels are registered using the "channel" parameter. Channels can be requested by their
162 More channels can be added by repeating the example above.
174 Another method of requesting channels is to request a channel with an empty string, Doing so
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| /Documentation/devicetree/bindings/hwmon/ |
| D | max6697.txt | 33 If not specified, alert will be enabled for all channels.
39 channels.
43 For MAX6581, resistance cancellation enabled for all channels if
47 channels.
51 channels.
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| /Documentation/devicetree/bindings/iio/ |
| D | iio-bindings.txt | 4 Sources of IIO channels can be represented by any node in the device
48 io-channels: List of phandle and IIO specifier pairs, one pair
56 order as the io-channels property. Consumers drivers
61 IIO channels from this node. Useful for bus nodes to provide
67 io-channels = <&adc 1>, <&ref 0>;
87 io-channels = <&adc 0>, <&adc 1>, <&adc 2>,
95 io-channels = <&adc 10>, <&adc 11>;
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