| /Documentation/devicetree/bindings/clock/ |
| D | sunxi.txt | 9 "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
13 "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
14 "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
15 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
16 "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
17 "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
18 "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
[all …]
|
| D | cirrus,lochnagar.txt | 26 "cirrus,lochnagar1-clk"
27 "cirrus,lochnagar2-clk"
47 - ln-clk-12m : On board fixed clock.
48 - ln-clk-11m : On board fixed clock.
49 - ln-clk-24m : On board fixed clock.
50 - ln-clk-22m : On board fixed clock.
51 - ln-clk-8m : On board fixed clock.
52 - ln-usb-clk-24m : On board fixed clock.
53 - ln-usb-clk-12m : On board fixed clock.
64 - ln-clk-12m : 12288000 Hz
[all …]
|
| D | nuvoton,npcm750-clk.txt | 22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
32 clk: clock-controller@f0801000 {
33 compatible = "nuvoton,npcm750-clk";
43 clk_refclk: clk-refclk {
51 clk_sysbypck: clk-sysbypck {
59 clk_mcbypck: clk-mcbypck {
67 clk_rg1refck: clk-rg1refck {
75 clk_rg2refck: clk-rg2refck {
82 clk_xin: clk-xin {
90 Example: GMAC controller node that consumes two clocks: a generated clk by the
[all …]
|
| D | sun8i-de2.txt | 6 - "allwinner,sun8i-a83t-de2-clk"
7 - "allwinner,sun8i-h3-de2-clk"
8 - "allwinner,sun8i-v3s-de2-clk"
9 - "allwinner,sun50i-a64-de2-clk"
10 - "allwinner,sun50i-h5-de2-clk"
11 - "allwinner,sun50i-h6-de3-clk"
25 compatible = "allwinner,sun8i-h3-de2-clk";
|
| D | altr_socfpga.txt | 12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
24 - div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
26 - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
28 value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
|
| D | sprd.txt | 8 - "sprd,sc9860-ap-clk"
12 - "sprd,sc9860-aonsecure-clk"
14 - "sprd,sc9860-gpu-clk"
15 - "sprd,sc9860-vsp-clk"
17 - "sprd,sc9860-cam-clk"
19 - "sprd,sc9860-disp-clk"
27 parents are in, since each clk node would represent many clocks
58 compatible = "sprd,sc9860-ap-clk";
|
| D | snps,pll-clock.txt | 17 input-clk: input-clk {
23 core-clk: core-clk@80 {
27 clocks = <&input-clk>;
|
| D | zx296702-clk.txt | 9 "zte,zx296702-topcrm-clk":
12 "zte,zx296702-lsp0crpm-clk" and
13 "zte,zx296702-lsp1crpm-clk":
24 compatible = "zte,zx296702-topcrm-clk";
|
| D | samsung,s2mps11.txt | 20 - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk",
21 "samsung,s2mps14-clk", "samsung,s5m8767-clk"
45 compatible = "samsung,s2mps11-clk";
|
| D | clps711x-clock.txt | 4 - compatible : Shall contain "cirrus,ep7209-clk".
16 compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
|
| D | hi6220-clock.txt | 19 - "hisilicon,hi6220-stub-clk"
28 - hisilicon,hi6220-clk-sram: phandle to the syscon managing the SoC internal sram;
43 compatible = "hisilicon,hi6220-stub-clk";
44 hisilicon,hi6220-clk-sram = <&sram>;
|
| D | csr,atlas7-car.txt | 11 The ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c
15 The ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c
|
| D | pistachio-clock.txt | 24 - compatible: Must be "img,pistachio-clk".
27 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
35 compatible = "img,pistachio-clk";
52 - compatible: Must be "img,pistachio-periph-clk".
56 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
63 compatible = "img,pistachio-clk-periph";
84 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
113 See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
| /Documentation/devicetree/bindings/clock/st/ |
| D | st,flexgen.txt | 78 clk_s_c0_flexgen: clk-s-c0-flexgen {
91 clock-output-names = "clk-icn-gpu",
92 "clk-fdma",
93 "clk-nand",
94 "clk-hva",
95 "clk-proc-stfe",
96 "clk-proc-tp",
97 "clk-rx-icn-dmu",
98 "clk-rx-icn-hva",
99 "clk-icn-cpu",
[all …]
|
| D | st,quadfs.txt | 34 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
41 clock-output-names = "clk-s-c0-fs0-ch0",
42 "clk-s-c0-fs0-ch1",
43 "clk-s-c0-fs0-ch2",
44 "clk-s-c0-fs0-ch3";
|
| D | st,clkgen.txt | 49 clk_s_a0_pll: clk-s-a0-pll {
55 clock-output-names = "clk-s-a0-pll-ofd-0";
58 clk_s_a0_flexgen: clk-s-a0-flexgen {
66 clock-output-names = "clk-ic-lmi0";
|
| /Documentation/devicetree/bindings/soc/amlogic/ |
| D | clk-measure.txt | 9 "amlogic,meson-gx-clk-measure" for GX SoCs
10 "amlogic,meson8-clk-measure" for Meson8 SoCs
11 "amlogic,meson8b-clk-measure" for Meson8b SoCs
12 "amlogic,meson-axg-clk-measure" for AXG SoCs
13 "amlogic,meson-g12a-clk-measure" for G12a SoCs
14 "amlogic,meson-sm1-clk-measure" for SM1 SoCs
19 compatible = "amlogic,meson-gx-clk-measure";
|
| /Documentation/devicetree/bindings/sound/ |
| D | qcom,lpass-cpu.txt | 10 * "ahbix-clk"
11 * "mi2s-osr-clk"
12 * "mi2s-bit-clk"
14 * "ahbix-clk"
19 * "pcnoc-mport-clk"
20 * "pcnoc-sway-clk"
45 clock-names = "ahbix-clk", "mi2s-osr-clk", "mi2s-bit-clk";
|
| /Documentation/driver-api/ |
| D | clk.rst | 2 The Common Clk Framework
7 This document endeavours to explain the common clk framework details,
9 detailed explanation of the clock api in include/linux/clk.h, but
15 The common clk framework is an interface to control the clock nodes
22 clk which unifies the framework-level accounting and infrastructure that
24 is a common implementation of the clk.h api, defined in
25 drivers/clk/clk.c. Finally there is struct clk_ops, whose operations
26 are invoked by the clk api implementation.
46 drivers/clk/clk.c, modified for brevity::
61 The members above make up the core of the clk tree topology. The clk
[all …]
|
| /Documentation/devicetree/bindings/arm/marvell/ |
| D | cp110-system-controller.txt | 92 mpp1 1 gpio, dev(ale0), au(i2sdo_spdifo), ge0(rxd2), tdm(drx), ptp(clk), mss_i2c(sck), uart0(txd), …
98 …, dev(ad10), ge0(txd2), spi0(csn1), spi1(csn1), sata0(present_act), led(data), uart0(txd), ptp(clk)
99 …9), ge0(txd1), spi0(csn0), spi1(csn0), uart0(cts), led(stb), uart2(rxd), ptp(pclk_out), synce1(clk)
100 mpp9 9 gpio, dev(ad8), ge0(txd0), spi0(mosi), spi1(mosi), pcie(rstoutn), synce2(clk)
102 mpp11 11 gpio, dev(wen1), ge0(txclkout), spi0(clk), spi1(clk), uart0(rts), led(clk), uart2(txd), sa…
107 mpp16 16 gpio, dev(ad6), spi1(clk), mss_spi(clk)
120 mpp29 29 gpio, dev(csn2), spi1(mosi), mss_gpio6, ge0(rxd1), spi0(csn6), pcie1(clkreq), ptp(clk), ms…
121 …ev(csn3), spi1(clk), mss_gpio7, ge0(rxd0), spi0(csn7), pcie0(clkreq), ptp(pclk_out), mss_i2c(sck),…
126 mpp35 35 gpio, sata1(present_act), i2c1(sda), mss_spi(clk), tdm(pclk), au(i2sdo_spdifo), sdio(card_…
127 mpp36 36 gpio, synce2(clk), i2c1(sck), ptp(clk), synce1(clk), au(i2sbclk), sata0(present_act), xg(m…
[all …]
|
| /Documentation/devicetree/bindings/i2c/ |
| D | nvidia,tegra20-i2c.txt | 29 - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and
30 fast-clk. Tegra114 has only one clock source called as div-clk and
46 - div-clk
47 - fast-clk
49 - div-clk
69 clock-names = "div-clk", "fast-clk";
|
| /Documentation/devicetree/bindings/net/ |
| D | stm32-dwmac.txt | 15 Should be "mac-clk-tx" for the MAC TX clock.
16 Should be "mac-clk-rx" for the MAC RX clock.
27 - st,eth-clk-sel (boolean) : set this property in RGMII PHY when you want to select RCC clock inste…
28 - st,eth-ref-clk-sel (boolean) : set this property in RMII mode when you have PHY without crystal …
38 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
|
| /Documentation/devicetree/bindings/spi/ |
| D | spi-mt65xx.txt | 35 - clock-names: shall be "parent-clk" for the parent clock, "sel-clk" for the
36 muxes clock, and "spi-clk" for the clock gate.
61 clock-names = "parent-clk", "sel-clk", "spi-clk";
|
| /Documentation/devicetree/bindings/arm/altera/ |
| D | socfpga-clk-manager.yaml | 4 $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
17 - const: altr,clk-mgr
27 compatible = "altr,clk-mgr";
|
| /Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,nvec.txt | 14 - div-clk
15 - fast-clk
17 - div-clk
|