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/Documentation/devicetree/bindings/clock/
Dfixed-factor-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Binding for simple fixed factor rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - allwinner,sun4i-a10-pll3-2x-clk
17 - fixed-factor-clock
19 "#clock-cells":
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Drenesas,h8300-div-clock.txt1 * Renesas H8/300 divider clock
5 - compatible: Must be "renesas,h8300-div-clock"
7 - clocks: Reference to the parent clocks ("extal1" and "extal2")
9 - #clock-cells: Must be 1
11 - reg: Base address and length of the divide rate selector
13 - renesas,width: bit width of selector
16 -------
19 compatible = "renesas,h8300-div-clock";
21 #clock-cells = <0>;
Daltr_socfpga.txt1 Device Tree Clock bindings for Altera's SoCFPGA platform
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
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Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
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Drenesas,emev2-smu.txt1 Device tree Clock bindings for Renesas EMMA Mobile EV2
3 This binding uses the common clock binding.
7 This is not a clock provider, but clocks under SMU depend on it.
10 - compatible: Should be "renesas,emev2-smu"
11 - reg: Address and Size of SMU registers
15 "Serial clock generator" in fig."Clock System Overview" of the manual,
17 This makes internal (neither input nor output) clock that is provided
21 - compatible: Should be "renesas,emev2-smu-clkdiv"
22 - reg: Byte offset from SMU base and Bit position in the register
23 - clocks: Parent clocks. Input clocks as described in clock-bindings.txt
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/Documentation/devicetree/bindings/clock/ti/
Dfixed-factor-clock.txt1 Binding for TI fixed factor rate clock sources.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1], and also uses the autoidle
6 support from TI autoidle clock [2].
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 [2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
12 - compatible : shall be "ti,fixed-factor-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - ti,clock-div: fixed divider.
15 - ti,clock-mult: fixed multiplier.
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Ddivider.txt1 Binding for TI divider clock
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1]. It assumes a
6 register-mapped adjustable clock rate divider that does not gate and has
7 only one input clock or parent. By default the value programmed into
17 ti,index-starts-at-one - valid divisor values start at 1, not the default
24 ti,index-power-of-two - valid divisor values are powers of two. E.g:
41 Any zero value in this array means the corresponding bit-value is invalid
52 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
53 [2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
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Dautoidle.txt1 Binding for Texas Instruments autoidle clock.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1]. It assumes a register mapped
6 clock which can be put to idle automatically by hardware based on the usage
7 and a configuration bit setting. Autoidle clock is never an individual
8 clock, it is always a derivative of some basic clock like a gate, divider,
9 or fixed-factor.
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - reg : offset for the register controlling the autoidle
15 - ti,autoidle-shift : bit shift of the autoidle enable bit
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Dcomposite.txt1 Binding for TI composite clock.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1]. It assumes a
6 register-mapped composite clock with multiple different sub-types;
8 a multiplexer clock with multiple input clock signals or parents, one
11 an adjustable clock rate divider, this behaves exactly as [3]
14 clock, this behaves exactly as [4]
17 merged to this clock. The component clocks shall be of one of the
18 "ti,*composite*-clock" types.
20 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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/Documentation/devicetree/bindings/i2c/
Dnvidia,tegra20-i2c.txt4 - compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
5 "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
6 For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
7 "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
10 nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
14 "nvidia,tegra20-i2c-dvc".
15 nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
16 master and slave mode of I2C communication. The i2c-tegra driver only
18 only compatible with "nvidia,tegra20-i2c".
19 nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
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Di2c-mt65xx.txt6 - compatible: value should be either of the following.
7 "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701
8 "mediatek,mt2712-i2c": for MediaTek MT2712
9 "mediatek,mt6577-i2c": for MediaTek MT6577
10 "mediatek,mt6589-i2c": for MediaTek MT6589
11 "mediatek,mt7622-i2c": for MediaTek MT7622
12 "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
13 "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
14 "mediatek,mt8173-i2c": for MediaTek MT8173
15 "mediatek,mt8183-i2c": for MediaTek MT8183
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/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,nvec.txt4 - compatible : should be "nvidia,nvec".
5 - reg : the iomem of the i2c slave controller
6 - interrupts : the interrupt line of the i2c slave controller
7 - clock-frequency : the frequency of the i2c bus
8 - gpios : the gpio used for ec request
9 - slave-addr: the i2c address of the slave controller
10 - clocks : Must contain an entry for each entry in clock-names.
11 See ../clocks/clock-bindings.txt for details.
12 - clock-names : Must include the following entries:
14 - div-clk
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/Documentation/devicetree/bindings/nios2/
Dnios2.txt11 - compatible: Compatible property value should be "altr,nios2-1.0".
12 - reg: Contains CPU index.
13 - interrupt-controller: Specifies that the node is an interrupt controller
14 - #interrupt-cells: Specifies the number of cells needed to encode an
16 - clock-frequency: Contains the clock frequency for CPU, in Hz.
17 - dcache-line-size: Contains data cache line size.
18 - icache-line-size: Contains instruction line size.
19 - dcache-size: Contains data cache size.
20 - icache-size: Contains instruction cache size.
21 - altr,pid-num-bits: Specifies the number of bits to use to represent the process
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/Documentation/devicetree/bindings/mmc/
Dexynos-dw-mshc.txt7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
27 unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
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/Documentation/devicetree/bindings/mfd/
Dsun6i-prcm.txt1 * Allwinner PRCM (Power/Reset/Clock Management) Multi-Functional Device
7 - compatible: "allwinner,sun6i-a31-prcm" or "allwinner,sun8i-a23-prcm"
8 - reg: The PRCM registers range
11 - see Documentation/devicetree/bindings/clock/sunxi.txt for clock devices
12 - see Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt for reset
19 compatible = "allwinner,sun6i-a31-prcm";
24 compatible = "allwinner,sun6i-a31-ar100-clk";
25 #clock-cells = <0>;
30 compatible = "fixed-factor-clock";
31 #clock-cells = <0>;
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/Documentation/devicetree/bindings/phy/
Dti-phy.txt6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
21 "power", "pcie_pcs" and "control_sma" for control-phy-pcie
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/Documentation/devicetree/bindings/leds/
Dleds-bcm6358.txt5 which can either be controlled by software (exporting the 74x164 as spi-gpio.
6 See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or
10 - compatible : should be "brcm,bcm6358-leds".
11 - #address-cells : must be 1.
12 - #size-cells : must be 0.
13 - reg : BCM6358 LED controller address and size.
16 - brcm,clk-div : SCK signal divider. Possible values are 1, 2, 4 and 8.
18 - brcm,clk-dat-low : Boolean, makes clock and data signals active low.
21 Each LED is represented as a sub-node of the brcm,bcm6358-leds device.
23 LED sub-node required properties:
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/Documentation/devicetree/bindings/clock/st/
Dst,flexgen.txt5 - a clock cross bar (represented by a mux element)
6 - a pre and final dividers (represented by a divider and gate elements)
13 -------------------------------------------------------------------
15 | --------------------------------------------- |
16 | | ------- -------- -------- | |
18 ---|-----------------|-->| | | | | | | |
20 | | ------- | | | |Pre | |Final | | |
22 | |->| | | | | | x32 | | x32 | | |
23 | | | odf_0|----|-->| | | | | | | |
28 | | ------- | | | | | | | | |
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/Documentation/devicetree/bindings/display/
Dssd1307fb.txt4 - compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for
7 - reg: Should contain address of the controller on the I2C bus. Most likely
9 - pwm: Should contain the pwm to use according to the OF device tree PWM
11 - solomon,height: Height in pixel of the screen driven by the controller
12 - solomon,width: Width in pixel of the screen driven by the controller
13 - solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
17 - reset-gpios: The GPIO used to reset the OLED display, if available. See
19 - vbat-supply: The supply for VBAT
20 - solomon,segment-no-remap: Display needs normal (non-inverted) data column
22 - solomon,com-seq: Display uses sequential COM pin configuration
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/Documentation/devicetree/bindings/iio/frequency/
Dadf4350.txt4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
10 ADF435x Reference Clock (CLKIN).
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
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/Documentation/hwmon/
Dw83781d.rst10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
12 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83781d.pdf
18 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
28 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83783s.pdf
34 Addresses scanned: I2C 0x28 - 0x2f
42 - Frodo Looijaard <frodol@dds.nl>,
43 - Philip Edelbrock <phil@netroedge.com>,
44 - Mark Studebaker <mdsxyz123@yahoo.com>
47 -----------------
67 -----------
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