Searched +full:clock +full:- +full:frequency (Results 1 – 25 of 428) sorted by relevance
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-ocores.txt | 1 Device tree configuration for i2c-ocores
4 - compatible : "opencores,i2c-ocores"
6 "sifive,fu540-c000-i2c", "sifive,i2c0"
8 FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
10 - reg : bus address start and address range size of device
11 - clocks : handle to the controller clock; see the note below.
12 Mutually exclusive with opencores,ip-clock-frequency
13 - opencores,ip-clock-frequency: frequency of the controller clock in Hz;
15 - #address-cells : should be <1>
16 - #size-cells : should be <0>
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| D | i2c-axxia.txt | 4 - compatible : Must be "lsi,api2c"
5 - reg : Offset and length of the register set for the device
6 - interrupts : the interrupt specifier
7 - #address-cells : Must be <1>;
8 - #size-cells : Must be <0>;
9 - clock-names : Must contain "i2c".
10 - clocks: Must contain an entry for each name in clock-names. See the common
11 clock bindings.
14 - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
15 the default 100 kHz frequency will be used. As only Normal and Fast modes
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| D | i2c-designware.txt | 5 - compatible : should be "snps,designware-i2c"
6 or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback
7 - reg : Offset and length of the register set for the device
8 - interrupts : <IRQ> where IRQ is the interrupt number.
9 - clocks : phandles for the clocks, see the description of clock-names below.
10 The phandle for the "ic_clk" clock is required. The phandle for the "pclk"
11 clock is optional. If a single clock is specified but no clock-name, it is
12 the "ic_clk" clock. If both clocks are listed, the "ic_clk" must be first.
16 - clock-frequency : desired I2C bus clock frequency in Hz.
20 - clock-names : Contains the names of the clocks:
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| /Documentation/devicetree/bindings/clock/ |
| D | silabs,si570.txt | 2 I2C clock generators.
5 This binding uses the common clock binding[1]. Details about the devices can be
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 http://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf
15 - compatible: Shall be one of "silabs,si570", "silabs,si571",
17 - reg: I2C device address.
18 - #clock-cells: From common clock bindings: Shall be 0.
19 - factory-fout: Factory set default frequency. This frequency is part specific.
20 The correct frequency for the part used has to be provided in
23 - temperature-stability: Temperature stability of the device in PPM. Should be
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| D | nvidia,tegra124-car.txt | 1 NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the
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| D | pwm-clock.txt | 1 Binding for an external clock signal driven by a PWM pin.
3 This binding uses the common clock binding[1] and the common PWM binding[2].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 - compatible : shall be "pwm-clock".
10 - #clock-cells : from common clock binding; shall be set to 0.
11 - pwms : from common PWM binding; this determines the clock frequency
15 - clock-output-names : From common clock binding.
16 - clock-frequency : Exact output frequency, in case the PWM period
20 clock {
21 compatible = "pwm-clock";
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| D | imx8mn-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8M Nano Clock Control Module Binding
10 - Anson Huang <Anson.Huang@nxp.com>
13 NXP i.MX8M Nano clock control module is an integrated clock controller, which
18 const: fsl,imx8mn-ccm
25 - description: 32k osc
26 - description: 24m osc
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| D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
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| D | qoriq-clock.txt | 1 * Clock Block on Freescale QorIQ Platforms
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
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| D | clps711x-clock.txt | 1 * Clock bindings for the Cirrus Logic CLPS711X CPUs
4 - compatible : Shall contain "cirrus,ep7209-clk".
5 - reg : Address of the internal register set.
6 - startup-frequency: Factory set CPU startup frequency in HZ.
7 - #clock-cells : Should be <1>.
9 The clock consumer should specify the desired clock by having the clock
10 ID in its "clocks" phandle cell. See include/dt-bindings/clock/clps711x-clock.h
11 for the full list of CLPS711X clock IDs.
15 #clock-cells = <1>;
16 compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
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| D | fixed-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Binding for simple fixed-rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
15 const: fixed-clock
17 "#clock-cells":
20 clock-frequency: true
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | mt9p031.txt | 1 * Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor
3 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor with
5 two-wire serial interface.
8 - compatible: value should be either one among the following
12 - input-clock-frequency: Input clock frequency.
14 - pixel-clock-frequency: Pixel clock frequency.
17 - reset-gpios: Chip reset GPIO
20 Documentation/devicetree/bindings/media/video-interfaces.txt.
30 reset-gpios = <&gpio3 30 0>;
34 input-clock-frequency = <6000000>;
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| D | toshiba,et8ek8.txt | 6 Documentation/devicetree/bindings/media/video-interfaces.txt .
10 --------------------
12 - compatible: "toshiba,et8ek8"
13 - reg: I2C address (0x3e, or an alternative address)
14 - vana-supply: Analogue voltage supply (VANA), 2.8 volts
15 - clocks: External clock to the sensor
16 - clock-frequency: Frequency of the external clock to the sensor. Camera
17 driver will set this frequency on the external clock. The clock frequency is
18 a pre-determined frequency known to be suitable to the board.
19 - reset-gpios: XSHUTDOWN GPIO. The XSHUTDOWN signal is active low. The sensor
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-sc18is602.txt | 4 - compatible : Should be one of
8 - reg: I2C bus address
11 - clock-frequency : external oscillator clock frequency. If not
12 specified, the SC18IS602 default frequency (7372000) will be used.
14 The clock-frequency property is relevant and needed only if the chip has an
22 clock-frequency = <14744000>;
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| D | spi_oc_tiny.txt | 4 - compatible : should be "opencores,tiny-spi-rtlsvn2".
5 - gpios : should specify GPIOs used for chipselect.
7 - clock-frequency : input clock frequency to the core.
8 - baud-width: width, in bits, of the programmable divider used to scale
9 the input clock to SCLK.
11 The clock-frequency and baud-width properties are needed only if the divider
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| /Documentation/devicetree/bindings/display/exynos/ |
| D | exynos_dsim.txt | 4 - compatible: value should be one of the following
5 "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
6 "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
7 "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
8 "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
9 "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
10 - reg: physical base address and length of the registers set for the device
11 - interrupts: should contain DSI interrupt
12 - clocks: list of clock specifiers, must contain an entry for each required
13 entry in clock-names
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| /Documentation/devicetree/bindings/iio/imu/ |
| D | adi,adis16480.txt | 6 - compatible: Must be one of
11 * "adi,adis16495-1"
12 * "adi,adis16495-2"
13 * "adi,adis16495-3"
14 * "adi,adis16497-1"
15 * "adi,adis16497-2"
16 * "adi,adis16497-3"
17 - reg: SPI chip select number for the device
18 - spi-max-frequency: Max SPI frequency to use
19 see: Documentation/devicetree/bindings/spi/spi-bus.txt
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| /Documentation/devicetree/bindings/net/wireless/ |
| D | ti,wlcore.txt | 8 - compatible: should be one of the following:
20 - interrupts : specifies attributes for the out-of-band interrupt.
23 - ref-clock-frequency : ref clock frequency in Hz
24 - tcxo-clock-frequency : tcxo clock frequency in Hz
26 Note: the *-clock-frequency properties assume internal clocks. In case of external
27 clock, new bindings (for parsing the clock nodes) have to be added.
32 vmmc-supply = <&wlan_en_reg>;
33 bus-width = <4>;
34 cap-power-off-card;
35 keep-power-in-suspend;
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| D | ti,wlcore,spi.txt | 7 - compatible : Should be one of the following:
18 - reg : Chip select address of device
19 - spi-max-frequency : Maximum SPI clocking speed of device in Hz
20 - interrupts : Should contain parameters for 1 interrupt line.
21 - vwlan-supply : Point the node of the regulator that powers/enable the
25 - ref-clock-frequency : Reference clock frequency (should be set for wl12xx)
26 - clock-xtal : boolean, clock is generated from XTAL
28 - Please consult Documentation/devicetree/bindings/spi/spi-bus.txt
38 spi-max-frequency = <48000000>;
39 interrupt-parent = <&gpio3>;
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| /Documentation/devicetree/bindings/net/can/ |
| D | cc770.txt | 8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
14 - interrupts : property with a value describing the interrupt source
19 - bosch,external-clock-frequency : frequency of the external oscillator
20 clock in Hz. Note that the internal clock frequency used by the
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
31 - bosch,disconnect-rx0-input : see data sheet.
33 - bosch,disconnect-rx1-input : see data sheet.
35 - bosch,disconnect-tx1-output : see data sheet.
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| D | sja1000.txt | 5 - compatible : should be one of "nxp,sja1000", "technologic,sja1000".
7 - reg : should specify the chip select, address offset and size required
10 - interrupts: property with a value describing the interrupt source
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
20 - nxp,external-clock-frequency : Frequency of the external oscillator
21 clock in Hz. Note that the internal clock frequency used by the
25 - nxp,tx-output-mode : operation mode of the TX output control logic:
26 <0x0> : bi-phase output mode
29 <0x3> : clock output mode
31 - nxp,tx-output-config : TX output pin configuration:
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| /Documentation/devicetree/bindings/usb/ |
| D | usb-nop-xceiv.txt | 4 - compatible: should be usb-nop-xceiv
5 - #phy-cells: Must be 0
8 - clocks: phandle to the PHY clock. Use as per Documentation/devicetree
9 /bindings/clock/clock-bindings.txt
10 This property is required if clock-frequency is specified.
12 - clock-names: Should be "main_clk"
14 - clock-frequency: the clock frequency (in Hz) that the PHY clock must
17 - vcc-supply: phandle to the regulator that provides power to the PHY.
19 - reset-gpios: Should specify the GPIO for reset.
21 - vbus-detect-gpio: should specify the GPIO detecting a VBus insertion
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| /Documentation/devicetree/bindings/sound/ |
| D | ak4642.txt | 7 - compatible : "asahi-kasei,ak4642" or "asahi-kasei,ak4643" or "asahi-kasei,ak4648"
8 - reg : The chip select number on the I2C bus
12 - #clock-cells : common clock binding; shall be set to 0
13 - clocks : common clock binding; MCKI clock
14 - clock-frequency : common clock binding; frequency of MCKO
15 - clock-output-names : common clock binding; MCKO clock name
21 compatible = "asahi-kasei,ak4642";
30 compatible = "asahi-kasei,ak4643";
32 #clock-cells = <0>;
34 clock-frequency = <12288000>;
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| /Documentation/devicetree/bindings/c6x/ |
| D | clocks.txt | 1 C6X PLL Clock Controllers
2 -------------------------
4 This is a first-cut support for the SoC clock controllers. This is still
6 clock support is added to the kernel.
10 - compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | vf610-adc.txt | 7 - compatible: Should contain "fsl,vf610-adc"
8 - reg: Offset and length of the register set for the device
9 - interrupts: Should contain the interrupt for the device
10 - clocks: The clock is needed by the ADC controller, ADC clock source is ipg clock.
11 - clock-names: Must contain "adc", matching entry in the clocks property.
12 - vref-supply: The regulator supply ADC reference voltage.
15 - fsl,adck-max-frequency: Maximum frequencies according to datasheets operating
17 - Frequency in normal mode (ADLPC=0, ADHSC=0)
18 - Frequency in high-speed mode (ADLPC=0, ADHSC=1)
19 - Frequency in low-power mode (ADLPC=1, ADHSC=0)
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