| /Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 1 * Core Clock bindings for Marvell MVEBU SoCs
3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
53 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
54 "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
55 "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
56 "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
57 "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
58 "marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
59 "marvell,dove-core-clock" - for Dove SoC core clocks
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| D | arm-integrator.txt | 1 Clock bindings for ARM Integrator and Versatile Core Module clocks
7 core module and there is only one of these.
9 This clock node *must* be a subnode of the core module, since
23 core-module@10000000 {
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| D | qoriq-clock.txt | 68 core PLLs are based on a different input clock from the
116 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
117 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
118 * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
119 * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
128 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
129 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
162 compatible = "fsl,qoriq-core-pll-1.0";
170 compatible = "fsl,qoriq-core-pll-1.0";
178 compatible = "fsl,qoriq-core-mux-1.0";
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| /Documentation/driver-api/ |
| D | sound.rst | 4 .. kernel-doc:: include/sound/core.h
13 .. kernel-doc:: sound/core/pcm.c
16 .. kernel-doc:: sound/core/device.c
19 .. kernel-doc:: sound/core/info.c
22 .. kernel-doc:: sound/core/rawmidi.c
25 .. kernel-doc:: sound/core/sound.c
28 .. kernel-doc:: sound/core/memory.c
31 .. kernel-doc:: sound/core/pcm_memory.c
34 .. kernel-doc:: sound/core/init.c
37 .. kernel-doc:: sound/core/isadma.c
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| /Documentation/x86/ |
| D | topology.rst | 80 - On AMD, the Node ID or Core Complex ID containing the Last Level
86 A core consists of 1 or more threads. It does not matter whether the threads
89 AMDs nomenclature for a CMT core is "Compute Unit". The kernel always uses
90 "core".
92 Core-related topology information in the kernel:
96 The number of threads in a core. The number of threads in a package can be
107 AMDs nomenclature for CMT threads is "Compute Unit Core". The kernel always
121 The cpumask contains all online threads in the core to which a thread
134 The ID of the core to which a thread belongs. It is also printed in /proc/cpuinfo
149 1) Single Package, Single Core::
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,c64x+megamod-pic.txt | 4 * C64X+ Core Interrupt Controller
6 The core interrupt controller provides 16 prioritized interrupts to the
7 C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
9 sources coming from outside the core.
13 - compatible: Should be "ti,c64x+core-pic";
18 Single cell specifying the core interrupt priority level (4-15) where
26 compatible = "ti,c64x+core-pic";
35 may be cascaded into the core interrupt controller. The megamodule PIC
36 has a total of 12 outputs cascading into the core interrupt controller.
37 One for each core interrupt priority level. In addition to the combined
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| /Documentation/kbuild/ |
| D | Kconfig.recursion-issue-01 | 13 # * What values are possible for CORE?
15 # CORE_BELL_A_ADVANCED selects CORE, which means that it influences the values
16 # that are possible for CORE. So for example if CORE_BELL_A_ADVANCED is 'y',
17 # CORE must be 'y' too.
27 # CORE_BELL_A depends on CORE, so CORE influences CORE_BELL_A.
30 # what values are possible for CORE we ended up needing to address questions
31 # regarding possible values of CORE itself again. Answering the original
32 # question of what are the possible values of CORE would make the kconfig
38 # of the "select CORE" from CORE_BELL_A_ADVANCED as that is implicit already
39 # since CORE_BELL_A depends on CORE. Recursive dependency issues are not always
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| D | Kconfig.recursion-issue-02 | 11 # drivers if they share a common core requirement and use disjoint semantics to
14 # core requirement, and one uses "select" while the other uses "depends on" to
19 # core requirements are not carefully synced, as drivers evolve features
24 # describes a simple driver core layout of example features a kernel might
25 # have. Let's assume we have some CORE functionality, then the kernel has a
32 # with CORE, one uses "depends on" while the other uses "select". Another
38 # To fix this the "depends on CORE" must be changed to "select CORE", or the
39 # "select CORE" must be changed to "depends on CORE".
49 config CORE config
54 depends on CORE
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| /Documentation/sound/kernel-api/ |
| D | alsa-driver-api.rst | 10 .. kernel-doc:: sound/core/init.c
14 .. kernel-doc:: sound/core/device.c
18 .. kernel-doc:: sound/core/sound.c
22 .. kernel-doc:: sound/core/memory.c
23 .. kernel-doc:: sound/core/memalloc.c
29 PCM Core
31 .. kernel-doc:: sound/core/pcm.c
32 .. kernel-doc:: sound/core/pcm_lib.c
33 .. kernel-doc:: sound/core/pcm_native.c
38 .. kernel-doc:: sound/core/pcm_misc.c
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| /Documentation/arm/ |
| D | marvel.rst | 28 Core:
68 Core:
93 Core:
113 Core:
121 Core:
132 Core:
141 Core:
164 Core:
165 Sheeva ARMv7 compatible Dual-core or Quad-core PJ4B-MP
179 Core:
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| /Documentation/devicetree/bindings/input/ |
| D | ps2keyb-mouse-apbps2.txt | 1 Aeroflex Gaisler APBPS2 PS/2 Core, supporting Keyboard or Mouse.
3 The APBPS2 PS/2 core is available in the GRLIB VHDL IP core library.
5 Note: In the ordinary environment for the APBPS2 core, a LEON SPARC system,
15 For further information look in the documentation for the GLIB IP core library:
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| /Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 14 When the WFI instruction is executed the ARM core would gate its internal
17 interrupt to trigger the core back in to active. This triggers the cache
26 Retention: Retention is a low power state where the core is clock gated and
27 the memory and the registers associated with the core are retained. The
35 to indicate a core entering a power down state without consulting any other
36 cpu or the system resources. This helps save power only on that core. The SPM
38 core, wait for the interrupt, restore power to the core, and ensure the
39 system state including cache hierarchy is ready before allowing core to
40 resume. Applying power and resetting the core causes the core to warmboot
45 be flushed in s/w, before powering down the core.
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| /Documentation/devicetree/bindings/usb/ |
| D | gr-udc.txt | 3 The GRUSBDC USB Device Controller core is available in the GRLIB VHDL
4 IP core library.
6 Note: In the ordinary environment for the core, a Leon SPARC system,
24 each OUT endpoint of the core. Fewer entries overrides the default sizes
30 each IN endpoint of the core. Fewer entries overrides the default sizes
33 For further information look in the documentation for the GLIB IP core library:
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| /Documentation/arm/samsung-s3c24xx/ |
| D | cpufreq.rst | 9 the ability to change the core, memory and peripheral operating
10 frequencies. The core control is exported via the CPUFreq driver
12 rate the core is running at.
19 ARM core is available as a separate driver.
25 The code core manages the CPU specific drivers, any data that they
31 The core registers with drivers/cpufreq at init time if all the data
54 The core code exports extra information via sysfs in the directory
62 information with the core driver to provide information about what the
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| /Documentation/target/ |
| D | tcm_mod_builder.rst | 32 …target:/mnt/sdb/lio-core-2.6.git/Documentation/target# python tcm_mod_builder.py -p iSCSI -m tcm_n…
33 tcm_dir: /mnt/sdb/lio-core-2.6.git/Documentation/target/../../
36 /mnt/sdb/lio-core-2.6.git/Documentation/target/../../drivers/target/tcm_nab5000
39 /mnt/sdb/lio-core-2.6.git/Documentation/target/../../drivers/target/tcm_nab5000
41 /mnt/sdb/lio-core-2.6.git/Documentation/target/../../drivers/target/tcm_nab5000/tcm_nab5000_base.h
43 /mnt/sdb/lio-core-2.6.git/Documentation/target/../../include/target/target_core_fabric_ops.h
45 …/mnt/sdb/lio-core-2.6.git/Documentation/target/../../drivers/target/tcm_nab5000/tcm_nab5000_fabric…
47 …/mnt/sdb/lio-core-2.6.git/Documentation/target/../../drivers/target/tcm_nab5000/tcm_nab5000_fabric…
49 …/mnt/sdb/lio-core-2.6.git/Documentation/target/../../drivers/target/tcm_nab5000/tcm_nab5000_config…
51 /mnt/sdb/lio-core-2.6.git/Documentation/target/../../drivers/target/tcm_nab5000/Kbuild
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| /Documentation/hid/ |
| D | hid-transport.rst | 14 devices and register them with the HID bus. HID core then loads generic device
16 transport and device setup/management. HID core is responsible of
36 | HID Core |
52 Everything below "HID Core" is simplified in this graph as it is only of
61 They allocate HID device objects and register them with HID core. Transport
62 drivers are not required to register themselves with HID core. HID core is never
67 device. Once a device is registered with HID core, the callbacks provided via
68 this struct are used by HID core to communicate with the device.
71 HID core will operate a device as long as it is registered regardless of any
73 must unregister the device from HID core and HID core will stop using the
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| /Documentation/hwmon/ |
| D | coretemp.rst | 5 * All Intel Core family
11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
12 - 0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
30 inside Intel CPUs. This driver can read both the per-core and per-package
49 tempX_input Core temperature (in millidegrees Celsius).
54 tempX_label Contains string "Core X", where X is processor
70 22nm Core i5/i7 Processors
81 32nm Core i3/i5/i7 Processors
88 32nm Core i7 Extreme Processors
103 45nm Xeon Processors 5400 Quad-Core
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| /Documentation/media/ |
| D | media_kapi.rst | 33 kapi/v4l2-core
34 kapi/dtv-core
35 kapi/rc-core
36 kapi/mc-core
37 kapi/cec-core
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| /Documentation/devicetree/bindings/media/ |
| D | qcom,venus.txt | 27 - "core" Core video accelerator clock
34 - "core" Core video accelerator clock
74 - "core" Subcore video accelerator clock
98 clock-names = "core", "iface", "bus";
106 clock-names = "core";
113 clock-names = "core";
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| D | img-ir-rev1.txt | 16 1st: Core clock (defaults to 32.768KHz if omitted).
22 "core": Core clock.
33 clock-names = "core";
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-grgpio.txt | 3 The GRGPIO GPIO core is available in the GRLIB VHDL IP core library.
5 Note: In the ordinary environment for the GRGPIO core, a Leon SPARC system,
25 For further information look in the documentation for the GLIB IP core library:
|
| /Documentation/devicetree/bindings/firmware/ |
| D | qcom,scm.txt | 25 * core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and
27 * core, iface and bus clocks required for "qcom,scm-apq8084",
29 - clock-names: Must contain "core" for the core clock, "iface" for the interface
42 clock-names = "core", "bus", "iface";
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| /Documentation/media/kapi/ |
| D | rc-core.rst | 6 Remote Controller core
9 The remote controller core implements infrastructure to receive and send
16 remote controller core is implemented on the top of the linux input/evdev
28 important part of the core is dedicated to adjust the driver and the core
63 The RC core also supports devices that have just IR emitters,
68 When the RC core receives events produced by ``RC_DRIVER_IR_RAW`` IR
70 corresponding scan code. The protocols supported by the RC core are
86 .. kernel-doc:: include/media/rc-core.h
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| /Documentation/media/uapi/cec/ |
| D | cec-ioc-g-mode.rst | 64 The CEC framework will process core messages unless requested otherwise
66 case, the CEC framework will pass on most core messages without
68 There are some messages that the core will always process, regardless of
69 the passthrough mode. See :ref:`cec-core-processing` for details.
155 to handle most core messages instead of relying on the CEC
204 Core message processing details:
208 .. _cec-core-processing:
210 .. flat-table:: Core Message Processing
218 - The core will return the CEC version that was set with
220 except when in passthrough mode. In passthrough mode the core
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| /Documentation/devicetree/bindings/dsp/ |
| D | fsl,dsp.yaml | 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8 DSP core
13 Some boards from i.MX8 family contain a DSP core used for
28 - description: core clock
34 - const: core
81 clock-names = "ipg", "ocram", "core";
|