Searched full:cores (Results 1 – 25 of 113) sorted by relevance
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| /Documentation/admin-guide/ |
| D | lockup-watchdogs.rst | 67 By default, the watchdog runs on all online cores. However, on a
69 on the housekeeping cores, not the cores specified in the "nohz_full"
71 the "nohz_full" cores, we would have to run timer ticks to activate
73 from protecting the user code on those cores from the kernel.
74 Of course, disabling it by default on the nohz_full cores means that
75 when those cores do enter the kernel, by default we will not be
77 to continue to run on the housekeeping (non-tickless) cores means
78 that we will continue to detect lockups properly on those cores.
80 In either case, the set of cores excluded from running the watchdog
82 nohz_full cores, this may be useful for debugging a case where the
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| /Documentation/devicetree/bindings/timer/ |
| D | snps,arc-timer.txt | 4 - Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically
5 TIMER0 used as clockevent provider (true for all ARC cores)
12 (16 for ARCHS cores, 3 for ARC700 cores)
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| D | ti,c64x+timer64.txt | 16 - ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | video.txt | 1 DT bindings for Xilinx video IP cores
4 Xilinx video IP cores process video streams by acting as video sinks and/or
10 cores are represented as defined in ../video-interfaces.txt.
18 The following properties are common to all Xilinx video IP cores.
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
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| D | xlnx,video.txt | 8 video IP cores. Each video IP core is represented as documented in video.txt
11 mappings between DMAs and the video IP cores.
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| /Documentation/devicetree/bindings/bus/ |
| D | brcm,bus-axi.txt | 9 The cores on the AXI bus are automatically detected by bcma with the
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
17 The top-level axi bus may contain children representing attached cores
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
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| /Documentation/ABI/testing/ |
| D | procfs-concurrent_time | 6 numbers for each uid, broken down by the total number of cores that were
15 of the core used by the uid's task and the number of cores associated
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| D | sysfs-bus-bcma | 14 There are a few types of BCMA cores, they can be identified by
22 BCMA cores of the same type can still slightly differ depending
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| D | debugfs-hisi-zip | 4 Description: Dump of compression cores related debug registers.
10 Description: Dump of decompression cores related debug registers.
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| /Documentation/ |
| D | percpu-rw-semaphore.txt | 9 cores take the lock for reading, the cache line containing the semaphore
10 is bouncing between L1 caches of the cores, causing performance
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| /Documentation/devicetree/bindings/display/etnaviv/ |
| D | etnaviv-drm.txt | 6 A more specific compatible is not needed, as the cores contain chip
11 - interrupts: Should contain the cores interrupt line
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| /Documentation/admin-guide/perf/ |
| D | arm_dsu_pmu.rst | 5 ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system,
11 cores connected to the same DSU. Like most of the other uncore PMUs, DSU
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| /Documentation/devicetree/bindings/power/ |
| D | renesas,apmu.txt | 22 - cpus: This node contains a list of CPU cores, which should match the order
23 of CPU cores used by the WUPCR and PSTR registers in the Advanced Power
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| /Documentation/x86/ |
| D | topology.rst | 24 threads, cores, packages, etc.
36 - cores
41 Packages contain a number of cores plus shared resources, e.g. DRAM
50 The number of cores in a package. This information is retrieved via CPUID.
59 and deduced from the APIC IDs of the cores in the package.
84 Cores chapter
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| /Documentation/admin-guide/device-mapper/ |
| D | unstriped.rst | 85 Intel NVMe drives contain two cores on the physical device.
88 in a 256k stripe across the two cores::
100 are striped across the two cores. When we unstripe this hardware RAID 0
113 unstriped ontop of Intel NVMe device that has 2 cores
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| /Documentation/devicetree/bindings/ |
| D | xilinx.txt | 1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
89 Some IP cores actually implement 2 or more logical devices. In
232 That covers the general approach to binding xilinx IP cores into the
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 4 RISC-V cores include Control Status Registers (CSRs) which are local to each
12 interrupts. Software interrupts are used to send IPIs between cores. The
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| D | snps,archs-intc.txt | 1 * ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)
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| D | openrisc,ompic.txt | 7 size is based on the number of cores the controller has been configured
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| /Documentation/devicetree/bindings/arc/ |
| D | axs103.txt | 5 HS38x cores.
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| /Documentation/devicetree/bindings/arm/rockchip/ |
| D | pmu.txt | 5 This includes the power to the CPU cores.
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| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci-of-dwcmshc.txt | 1 * Synopsys DesignWare Cores Mobile Storage Host Controller
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| /Documentation/devicetree/bindings/arm/amlogic/ |
| D | pmu.txt | 5 This includes the power to the CPU cores.
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| /Documentation/devicetree/bindings/usb/ |
| D | iproc-udc.txt | 5 on Synopsys Designware Cores AHB Subsystem Device Controller
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| /Documentation/devicetree/bindings/sram/ |
| D | milbeaut-smp-sram.txt | 3 Milbeaut SoCs use a part of the sram for the bringup of the secondary cores.
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