Searched +full:cortex +full:- +full:a15 +full:- +full:timer (Results 1 – 4 of 4) sorted by relevance
| /Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ARM architected timer 10 - Marc Zyngier <marc.zyngier@arm.com> 11 - Mark Rutland <mark.rutland@arm.com> 13 ARM cores may have a per-core architected timer, which provides per-cpu timers, 14 or a memory mapped architected timer, which provides up to 8 frames with a 15 physical and optional virtual timer per frame. [all …]
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| D | nxp,sysctr-timer.txt | 4 a shared time base to Cortex A15, A7, A53, A73, etc. it is intended for use in 6 unrelated clocks. The compare frame inside can be used for timer purpose. 10 - compatible : should be "nxp,sysctr-timer" 11 - reg : Specifies the base physical address and size of the comapre 13 - interrupts : should be the first compare frames' interrupt 14 - clocks : Specifies the counter clock. 15 - clock-names: Specifies the clock's name of this module 19 system_counter: timer@306a0000 { 20 compatible = "nxp,sysctr-timer"; 21 reg = <0x306a0000 0x20000>;/* system-counter-rd & compare */ [all …]
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| /Documentation/devicetree/bindings/arm/ |
| D | cpu-capacity.txt | 6 1 - Introduction 15 2 - CPU capacity definition 19 heterogeneity. Such heterogeneity can come from micro-architectural differences 23 capture a first-order approximation of the relative performance of CPUs. 29 * A "single-threaded" or CPU affine benchmark 43 3 - capacity-dmips-mhz 46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value 51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu 54 available, final capacities are calculated by directly using capacity-dmips- 58 4 - Examples [all …]
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| D | idle-states.txt | 6 1 - Introduction 10 where cores can be put in different low-power states (ranging from simple 12 the range of dynamic idle states that a processor can enter at run-time, can be 19 - Running 20 - Idle_standby 21 - Idle_retention 22 - Sleep 23 - Off 29 wake-up capabilities, hence it is not considered in this document). 39 2 - idle-states definitions [all …]
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