Searched +full:cortex +full:- +full:a9 +full:- +full:gic (Results 1 – 5 of 5) sorted by relevance
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
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| D | marvell,armada-370-xp-mpic.txt | 2 -----------------------------------------------------
5 - compatible: Should be "marvell,mpic"
6 - interrupt-controller: Identifies the node as an interrupt controller.
7 - msi-controller: Identifies the node as an PCI Message Signaled
9 - #interrupt-cells: The number of cells to define the interrupts. Should be 1.
12 - reg: Should contain PMIC registers location and length. First pair
13 for the main interrupt registers, second pair for the per-CPU
21 - interrupts: If defined, then it indicates that this MPIC is
24 connected as a slave to the Cortex-A9 GIC. The provided interrupt
25 indicate to which GIC interrupt the MPIC output is connected.
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,twd.txt | 3 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
4 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
7 The TWD is usually attached to a GIC to deliver its two per-processor
12 - compatible : Should be one of:
13 "arm,cortex-a9-twd-timer"
14 "arm,cortex-a5-twd-timer"
15 "arm,arm11mp-twd-timer"
17 - interrupts : One interrupt to each core
19 - reg : Specify the base address and the size of the TWD timer
24 - always-on : a boolean property. If present, the timer is powered through
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| /Documentation/devicetree/bindings/arm/ux500/ |
| D | boards.txt | 1 ST-Ericsson Ux500 boards
2 ------------------------
5 compatible = "st-ericsson,mop500" (legacy)
6 compatible = "st-ericsson,u8500"
10 soc: represents the system-on-chip and contains the chip
20 compatible = "ste,dbx500-backupram"
25 interrupt-controller:
26 see binding for interrupt-controller/arm,gic.txt
36 /dts-v1/;
39 model = "ST-Ericsson HREF (pre-v60) and ST UIB";
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| /Documentation/devicetree/bindings/arm/ |
| D | vexpress.txt | 2 -----------------------------------
16 ---------
19 - compatible value:
23 - for Coretile Express A5x2 (V2P-CA5s):
24 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
25 - for Coretile Express A9x4 (V2P-CA9):
26 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
32 - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1:
33 compatible = "arm,vexpress,v2p-ca15,tc1", \
34 "arm,vexpress,v2p-ca15", "arm,vexpress";
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