Searched full:counter (Results 1 – 25 of 229) sorted by relevance
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-counter | 1 What: /sys/bus/counter/devices/counterX/countY/count
7 What: /sys/bus/counter/devices/counterX/countY/ceiling
12 respective counter.
14 What: /sys/bus/counter/devices/counterX/countY/floor
19 respective counter.
21 What: /sys/bus/counter/devices/counterX/countY/count_mode
36 to the Count Y floor value. The counter freezes at
43 The counter is disabled whenever a counter overflow or
44 underflow takes place. The counter is re-enabled when a
45 new count value is loaded to the counter via a preset
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| D | sysfs-bus-iio-counter-104-quad-8 | 9 This interface is deprecated; please use the Counter subsystem.
11 Discrete set of available values for the respective counter
18 This interface is deprecated; please use the Counter subsystem.
31 counter freezes at count = preset when counting up, and
37 Counter is disabled whenever a 24-bit count overflow or
38 underflow takes place. The counter is re-enabled when a
39 new count value is loaded to the counter via a preset
44 The counter is reset to 0 at count = preset when
45 counting up, while the counter is set to the preset
46 value at count = 0 when counting down; the counter does
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| D | sysfs-bus-counter-ftm-quaddec | 1 What: /sys/bus/counter/devices/counterX/countY/prescaler_available
9 What: /sys/bus/counter/devices/counterX/countY/prescaler
14 On the FlexTimer, the counter clock source passes through a
15 prescaler (i.e. a counter). This acts like a clock
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| D | sysfs-bus-counter-104-quad-8 | 1 What: /sys/bus/counter/devices/counterX/signalY/index_polarity
8 What: /sys/bus/counter/devices/counterX/signalY/index_polarity_available
9 What: /sys/bus/counter/devices/counterX/signalY/synchronous_mode_available
16 What: /sys/bus/counter/devices/counterX/signalY/synchronous_mode
20 Configure the counter associated with Signal Y for
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| D | sysfs-bus-iio-timer-stm32 | 8 - "enable" : The Counter Enable signal CNT_EN is used
36 | Prescaler +-> | Counter | +-> | Master | TRGO(2)
89 When counting up the counter starts from 0 and fires an
91 When counting down the counter start from preset value
104 Configure the device counter enable modes, in all case
106 attribute and the counter is clocked by the internal clock.
108 Counter is always ON.
129 Configure the device counter trigger mode
131 attribute and the counter is clocked by the connected trigger
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| /Documentation/driver-api/ |
| D | generic-counter.rst | 4 Generic Counter Interface
10 Counter devices are prevalent within a diverse spectrum of industries.
13 resolve the issue of duplicate code found among existing counter device
14 drivers by introducing a generic counter interface for consumption. The
15 Generic Counter interface enables drivers to support and expose a common
16 set of components and functionality present in counter devices.
21 Counter devices can vary greatly in design, but regardless of whether
23 counter devices consist of a core set of components. This core set of
24 components, shared by all counter devices, is what forms the essence of
25 the Generic Counter interface.
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| /Documentation/devicetree/bindings/timer/ |
| D | nxp,sysctr-timer.txt | 1 NXP System Counter Module(sys_ctr)
3 The system counter(sys_ctr) is a programmable system counter which provides
5 applications where the counter is always powered and support multiple,
12 frame and the counter control, read & compare.
14 - clocks : Specifies the counter clock.
21 reg = <0x306a0000 0x20000>;/* system-counter-rd & compare */
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| D | fsl,ftm-timer.txt | 14 o "ftm-evt-counter-en"
15 o "ftm-src-counter-en"
25 "ftm-evt-counter-en", "ftm-src-counter-en";
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| D | arm,arch_timer.yaml | 44 description: The frequency of the main counter, in Hz. Should be present
57 that reading the counter is unreliable unless the same value is returned
59 to the implicit counter read.
66 the tval registers, due to the implicit counter read.
77 description: The main counter does not tick when the system is in
79 Architecture Reference Manual's specification that the system counter "must
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| D | brcm,bcm2835-system-timer.txt | 4 single 64-bit free running counter. Each channel has an output compare
6 free running counter values, and generates an interrupt.
13 - clock-frequency : The frequency of the clock that drives the counter, in Hz.
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| D | ti,keystone-timer.txt | 9 It is global timer is a free running up-counter and can generate interrupt
10 when the counter reaches preset counter values.
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| D | nxp,tpm-timer.txt | 5 management applications. The counter, compare and capture registers
7 power modes. TPM can support global counter bus where one TPM drives
8 the counter bus for the others, provided bit width is the same.
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| D | ti,davinci-timer.txt | 9 The timer is a free running up-counter and can generate interrupts when the
10 counter reaches preset counter values.
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| /Documentation/devicetree/bindings/counter/ |
| D | stm32-lptimer-cnt.txt | 1 STMicroelectronics STM32 Low-Power Timer quadrature encoder and counter
3 STM32 Low-Power Timer provides several counter modes. It can be used as:
6 - simple counter from IN1 input signal.
12 - compatible: Must be "st,stm32-lptimer-counter".
23 counter {
24 compatible = "st,stm32-lptimer-counter";
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| D | ftm-quaddec.txt | 1 FlexTimer Quadrature decoder counter
3 This driver exposes a simple counter for the quadrature decoder mode.
13 counter0: counter@29d0000 {
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| D | stm32-timer-cnt.txt | 11 - compatible: Must be "st,stm32-timer-counter".
26 counter {
27 compatible = "st,stm32-timer-counter";
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| /Documentation/admin-guide/perf/ |
| D | imx-ddr.rst | 7 counters is implemented. This is controlled by the CSV modes programed in counter
10 Selection of the value for each counter is done via the config registers. There
11 is one register for each counter. Counter 0 is special in that it always counts
13 interrupt is raised. If any other counter overflows, it continues counting, and
37 AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter.
38 When non-masked bits are matching corresponding AXI_ID bits then counter is
39 incremented. Perf counter is incremented if
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| /Documentation/devicetree/bindings/mfd/ |
| D | stm32-timers.txt | 4 - advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable
6 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a
8 - basic timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.
31 - counter: See ../counter/stm32-timer-cnt.txt
53 counter {
54 compatible = "st,stm32-timer-counter";
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| D | stm32-lptimer.txt | 6 - Quadrature encoder, counter
19 - counter: See ../counter/stm32-lptimer-cnt.txt
43 counter {
44 compatible = "st,stm32-lptimer-counter";
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | counter.txt | 1 OMAP Counter-32K bindings
6 - ti,hwmods: Name of the hwmod associated to the counter, which is typically
11 counter32k: counter@4a304000 {
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| /Documentation/core-api/ |
| D | atomic_ops.rst | 8 maintainers on how to implement atomic counter, bitops, and spinlock
19 typedef struct { int counter; } atomic_t;
20 typedef struct { long counter; } atomic_long_t;
22 Historically, counter has been declared volatile. This is now discouraged.
26 local_t is very similar to atomic_t. If the counter is per CPU and only
35 #define atomic_set(v, i) ((v)->counter = (i))
52 struct foo { atomic_t counter; };
60 atomic_set(&k->counter, 0);
70 #define atomic_read(v) ((v)->counter)
72 which simply reads the counter value currently visible to the calling thread.
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| /Documentation/w1/slaves/ |
| D | w1_ds2423.rst | 6 * Maxim DS2423 based counter devices.
23 Result of each page is provided as an ASCII output where each counter
26 Each lines will contain the values of 42 bytes read from the counter and
30 a counter value expressed as an integer after c=
35 - 4 bytes for the counter value
40 - c=<int> current counter value
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| /Documentation/riscv/ |
| D | pmu.rst | 24 * Interrupt caused by counter overflow
28 interrupt indicator is required for software to tell which counter has
128 It does NOT deal with the binding between an event and a physical counter,
135 for each hardware counter that triggered this overflow
137 get the event of this counter
147 set the counter appropriately for the next overflow
165 counter (event->count), but also updates the left period to the next interrupt
170 has to set the counter to a good value for the next interrupt; 2) inside the IRQ
171 it should set the counter to the same resonable value.
181 starts/stop the counter of some event in the PMU. All of them take the same
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| /Documentation/timers/ |
| D | timekeeping.rst | 30 Typically the clock source is a monotonic, atomic counter which will provide
41 the counter register is read in two phases on the bus lowest 16 bits first
42 and the higher 16 bits in a second bus cycle with the counter bits
44 values from the counter.
54 The clock source struct shall provide means to translate the provided counter
72 location, bit width, a parameter telling whether the counter in the
76 Since a 32-bit counter at say 100 MHz will wrap around to zero after some 43
80 code knows when the counter will wrap around and can insert the necessary
115 implementation is not provided, the system jiffy counter will be used as
147 counter to derive a 64-bit nanosecond value, so for example on the ARM
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| /Documentation/devicetree/bindings/pwm/ |
| D | pwm-fsl-ftm.txt | 27 "ftm_sys" (module clock, also can be used as counter clock),
28 "ftm_ext" (external counter clock),
29 "ftm_fix" (fixed counter clock),
30 "ftm_cnt_clk_en" (external and fixed counter clock enable/disable).
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