Searched +full:cpu +full:- +full:core (Results 1 – 25 of 234) sorted by relevance
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| /Documentation/x86/ |
| D | topology.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
35 - packages
36 - cores
37 - threads
46 Package-related topology information in the kernel:
48 - cpuinfo_x86.x86_max_cores:
52 - cpuinfo_x86.x86_max_dies:
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
17 The bottom hierarchy level sits at core or thread level depending on whether
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
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| /Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
6 The idle states supported by the QCOM SoC are defined as -
14 When the WFI instruction is executed the ARM core would gate its internal
17 interrupt to trigger the core back in to active. This triggers the cache
20 cache hierarchy is also out of standby, and then the cpu is allowed to resume
26 Retention: Retention is a low power state where the core is clock gated and
27 the memory and the registers associated with the core are retained. The
30 sequence and would wait for interrupt, before restoring the cpu to execution
33 Standalone PC: A cpu can power down and warmboot if there is a sufficient time
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| /Documentation/arm/samsung-s3c24xx/ |
| D | cpufreq.rst | 6 ------------
9 the ability to change the core, memory and peripheral operating
10 frequencies. The core control is exported via the CPUFreq driver
12 rate the core is running at.
14 There are two forms of the driver depending on the specific CPU and
19 ARM core is available as a separate driver.
23 ------
25 The code core manages the CPU specific drivers, any data that they
27 system. Each CPU registers a driver to control the PLL, clock dividers
31 The core registers with drivers/cpufreq at init time if all the data
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| /Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 1 * Core Clock bindings for Marvell MVEBU SoCs
3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
9 1 = cpuclk (CPU clock)
16 1 = cpuclk (CPU clock)
22 1 = cpuclk (CPU clock)
28 1 = cpuclk (CPU clock)
36 1 = cpuclk (CPU clock)
52 - compatible : shall be one of the following:
53 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
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| D | armada3700-periph-clock.txt | 14 -----------------------------------
31 16 cpu CPU
35 -----------------------------------
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
37 1 gbe-core parent clock for Gigabit Ethernet core
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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| /Documentation/hwmon/ |
| D | k8temp.rst | 19 -----------
23 from revision F of K8 core, but in fact it seems to be implemented for all
24 revisions of K8 except the first two revisions (SH-B0 and SH-B3).
26 Please note that you will need at least lm-sensors 2.10.1 for proper userspace
29 There can be up to four temperature sensors inside single CPU. The driver
30 will auto-detect the sensors and will display only temperatures from
36 temp1_input temperature of Core 0 and "place" 0
37 temp2_input temperature of Core 0 and "place" 1
38 temp3_input temperature of Core 1 and "place" 0
39 temp4_input temperature of Core 1 and "place" 1
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| /Documentation/devicetree/bindings/nds32/ |
| D | cpus.txt | 4 representation of a Andestech Processor Core, which is the root node in the
9 - compatible:
14 one of the following identifiers for a particular CPU core:
20 - device_type
23 Definition: must be "cpu"
24 - reg: Contains CPU index.
25 - clock-frequency: Contains the clock frequency for CPU, in Hz.
31 cpu@0 {
32 device_type = "cpu";
35 clock-frequency = <60000000>
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| /Documentation/devicetree/bindings/mips/img/ |
| D | xilfpga.txt | 4 Under the Imagination University Program, a microAptiv UP core has been
7 As we are dealing with a MIPS core instantiated on an FPGA, specifications
14 the ARTIX-7 FPGA by Xilinx.
18 - microAptiv UP core m14Kc
19 - 50MHz clock speed
20 - 128Mbyte DDR RAM at 0x0000_0000
21 - 8Kbyte RAM at 0x1000_0000
22 - axi_intc at 0x1020_0000
23 - axi_uart16550 at 0x1040_0000
24 - axi_gpio at 0x1060_0000
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| /Documentation/admin-guide/pm/ |
| D | cpufreq.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 CPU Performance Scaling
16 The Concept of CPU Performance Scaling
21 Operating Performance Points or P-states (in ACPI terminology). As a rule,
23 can be retired by the CPU over a unit of time, but also the higher the clock
25 time (or the more power is drawn) by the CPU in the given P-state. Therefore
26 there is a natural tradeoff between the CPU capacity (the number of instructions
27 that can be executed over a unit of time) and the power drawn by the CPU.
30 as possible and then there is no reason to use any P-states different from the
31 highest one (i.e. the highest-performance frequency/voltage configuration
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| D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 .. |cpufreq| replace:: :doc:`CPU Performance Scaling <cpufreq>`
8 CPU Idle Time Management
27 CPU idle time management is an energy-efficiency feature concerned about using
31 ------------
33 CPU idle time management operates on CPUs as seen by the *CPU scheduler* (that
37 software as individual single-core processors. In other words, a CPU is an
43 program) at a time, it is a CPU. In that case, if the hardware is asked to
46 Second, if the processor is multi-core, each core in it is able to follow at
52 enter an idle state, that applies to the core that asked for it in the first
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| D | intel_pstate.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 ``intel_pstate`` CPU Performance Scaling Driver
17 :doc:`CPU performance scaling subsystem <cpufreq>` in the Linux kernel
24 For the processors supported by ``intel_pstate``, the P-state concept is broader
27 information about that). For this reason, the representation of P-states used
29 refer to Intel Software Developer’s Manual [2]_). However, the ``CPUFreq`` core
32 ``intel_pstate`` maps its internal representation of P-states to frequencies too
34 practical for ``intel_pstate`` to supply the ``CPUFreq`` core with a table of
36 that. Some functionality of the core is limited by that.
38 Since the hardware P-state selection interface used by ``intel_pstate`` is
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| /Documentation/devicetree/bindings/x86/ |
| D | ce4100.txt | 2 ---------------------------
4 The CE4100 SoC uses for in core peripherals the following compatible
5 format: <vendor>,<chip>-<device>.
10 The CPU nodes
11 -------------
14 #address-cells = <1>;
15 #size-cells = <0>;
17 cpu@0 {
18 device_type = "cpu";
23 cpu@2 {
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| /Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-pmc.txt | 7 modes. It provides power-gating controllers for SoC and CPU power-islands.
10 - name : Should be pmc
11 - compatible : Should contain one of the following:
12 For Tegra20 must contain "nvidia,tegra20-pmc".
13 For Tegra30 must contain "nvidia,tegra30-pmc".
14 For Tegra114 must contain "nvidia,tegra114-pmc"
15 For Tegra124 must contain "nvidia,tegra124-pmc"
16 For Tegra132 must contain "nvidia,tegra124-pmc"
17 For Tegra210 must contain "nvidia,tegra210-pmc"
18 - reg : Offset and length of the register set for the device
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| /Documentation/cpu-freq/ |
| D | cpu-drivers.txt | 1 CPU frequency and voltage scaling code in the Linux(TM) kernel
8 - information for developers -
19 the clock speed, the less power the CPU consumes.
23 ---------
26 1.2 Per-CPU Initialization
39 So, you just got a brand-new CPU / chipset with datasheets and want to
40 add cpufreq support for this CPU / chipset? Great. Here are some hints
45 ------------------
48 function check whether this kernel runs on the right CPU and the right
49 chipset. If so, register a struct cpufreq_driver with the CPUfreq core
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| D | core.txt | 1 CPU frequency and voltage scaling code in the Linux(TM) kernel
18 the clock speed, the less power the CPU consumes.
22 ---------
23 1. CPUFreq core and interfaces
30 The CPUFreq core code is located in drivers/cpufreq/cpufreq.c. This
43 correctly registered with the core, and will not be unloaded until
53 There are two different CPUFreq notifiers - policy notifiers and
58 ----------------------------
72 --------------------------------
74 These are notified twice for each online CPU in the policy, when the
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| D | index.txt | 1 CPU frequency and voltage scaling code in the Linux(TM) kernel
15 the clock speed, the less power the CPU consumes.
20 ----------------------------
22 amd-powernow.txt - AMD powernow driver specific file.
24 core.txt - General description of the CPUFreq core and
27 cpu-drivers.txt - How to implement a new cpufreq processor driver.
29 cpufreq-nforce2.txt - nVidia nForce2 platform specific file.
31 cpufreq-stats.txt - General description of sysfs cpufreq stats.
33 index.txt - File index, Mailing list and Links (this document)
35 pcc-cpufreq.txt - PCC cpufreq driver specific file.
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| /Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 4 representation of a Nios II Processor Core.
11 - compatible: Compatible property value should be "altr,nios2-1.0".
12 - reg: Contains CPU index.
13 - interrupt-controller: Specifies that the node is an interrupt controller
14 - #interrupt-cells: Specifies the number of cells needed to encode an
16 - clock-frequency: Contains the clock frequency for CPU, in Hz.
17 - dcache-line-size: Contains data cache line size.
18 - icache-line-size: Contains instruction line size.
19 - dcache-size: Contains data cache size.
20 - icache-size: Contains instruction cache size.
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| /Documentation/admin-guide/ |
| D | cputopology.rst | 2 How CPU topology info is exported via sysfs
5 Export CPU topology info via sysfs. Items (attributes) are similar
7 /sys/devices/system/cpu/cpuX/topology/:
17 the CPU die ID of cpuX. Typically it is the hardware platform's
23 the CPU core ID of cpuX. Typically it is the hardware platform's
41 internal kernel map of CPUs within the same core.
46 human-readable list of CPUs within the same core.
56 human-readable list of CPUs sharing the same physical_package_id.
65 human-readable list of CPUs within the same die.
74 human-readable list of cpuX's hardware threads within the same
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| /Documentation/devicetree/bindings/timer/ |
| D | jcore,pit.txt | 1 J-Core Programmable Interval Timer and Clocksource
5 - compatible: Must be "jcore,pit".
7 - reg: Memory region(s) for timer/clocksource registers. For SMP,
8 there should be one region per cpu, indexed by the sequential,
9 zero-based hardware cpu number.
11 - interrupts: An interrupt to assign for the timer. The actual pit
12 core is integrated with the aic and allows the timer interrupt
|
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | jcore,aic.txt | 1 J-Core Advanced Interrupt Controller
5 - compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
7 the "aic2" core with 64 interrupts.
9 - reg: Memory region(s) for configuration. For SMP, there should be one
10 region per cpu, indexed by the sequential, zero-based hardware cpu
13 - interrupt-controller: Identifies the node as an interrupt controller
15 - #interrupt-cells: Specifies the number of cells needed to encode an
21 aic: interrupt-controller@200 {
24 interrupt-controller;
25 #interrupt-cells = <1>;
|
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
6 Some of these CSRs are used to control local interrupts connected to the core.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
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| /Documentation/scheduler/ |
| D | sched-bwc.rst | 5 [ This document only discusses CPU bandwidth control for SCHED_NORMAL.
6 The SCHED_RT case is covered in Documentation/scheduler/sched-rt-group.rst ]
9 specification of the maximum CPU bandwidth available to a group or hierarchy.
13 microseconds of CPU time. That quota is assigned to per-cpu run queues in
21 is transferred to cpu-local "silos" on a demand basis. The amount transferred
25 ----------
26 Quota and period are managed within the cpu subsystem via cgroupfs.
28 cpu.cfs_quota_us: the total available run-time within a period (in microseconds)
29 cpu.cfs_period_us: the length of a period (in microseconds)
30 cpu.stat: exports throttling statistics [explained further below]
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| /Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,nsp-cpu-method.txt | 1 Broadcom Northstar Plus SoC CPU Enable Method
2 ---------------------------------------------
4 CPU in the following Broadcom SoCs:
8 properties in the corresponding secondary "cpu" device tree node:
9 - enable-method = "brcm,bcm-nsp-smp";
10 - secondary-boot-reg = <...>;
12 The secondary-boot-reg property is a u32 value that specifies the
14 entry point for a secondary CPU. This entry is cpu node specific
15 and should be added per cpu. E.g., in case of NSP (BCM58625) which
16 is a dual core CPU SoC, this entry should be added to cpu1 node.
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| /Documentation/devicetree/bindings/arm/ |
| D | coresight-cpu-debug.txt | 1 * CoreSight CPU Debug Component:
3 CoreSight CPU debug component are compliant with the ARMv8 architecture
5 external debug module is mainly used for two modes: self-hosted debug and
7 and eventually the debug module connects with CPU for debugging. And the
8 debug module provides sample-based profiling extension, which can be used
9 to sample CPU program counter, secure state and exception level, etc;
10 usually every CPU has one dedicated debug module to be connected.
14 - compatible : should be "arm,coresight-cpu-debug"; supplemented with
18 - reg : physical base address and length of the register set.
20 - clocks : the clock associated to this component.
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