Searched +full:cpu +full:- +full:idle +full:- +full:states (Results 1 – 25 of 43) sorted by relevance
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| /Documentation/devicetree/bindings/arm/ |
| D | idle-states.txt | 2 ARM idle states binding description
6 1 - Introduction
10 where cores can be put in different low-power states (ranging from simple
11 wfi to power gating) according to OS PM policies. The CPU states representing
12 the range of dynamic idle states that a processor can enter at run-time, can be
14 to enter/exit specific idle states on a given processor.
17 power states an ARM CPU can be put into are identified by the following list:
19 - Running
20 - Idle_standby
21 - Idle_retention
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| D | cpu-capacity.txt | 6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
31 * Not subject to dynamic frequency scaling of the CPU
36 CPU capacities are obtained by running the Dhrystone benchmark on each CPU at
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| D | coresight-cpu-debug.txt | 1 * CoreSight CPU Debug Component:
3 CoreSight CPU debug component are compliant with the ARMv8 architecture
5 external debug module is mainly used for two modes: self-hosted debug and
7 and eventually the debug module connects with CPU for debugging. And the
8 debug module provides sample-based profiling extension, which can be used
9 to sample CPU program counter, secure state and exception level, etc;
10 usually every CPU has one dedicated debug module to be connected.
14 - compatible : should be "arm,coresight-cpu-debug"; supplemented with
18 - reg : physical base address and length of the register set.
20 - clocks : the clock associated to this component.
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| D | psci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
15 processors") can be used by Linux to initiate various CPU-centric power
18 Issue A of the specification describes functions for CPU suspend, hotplug
25 r0 => 32-bit Function ID / return value
26 {r1 - r3} => Parameters
37 - description:
41 - description:
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| /Documentation/devicetree/bindings/powerpc/opal/ |
| D | power-mgt.txt | 1 IBM Power-Management Bindings
5 idle states. The description of these idle states is exposed via the
6 node @power-mgt in the device-tree by the firmware.
9 ----------------
10 Typically each idle state has the following associated properties:
12 - name: The name of the idle state as defined by the firmware.
14 - flags: indicating some aspects of this idle states such as the
15 extent of state-loss, whether timebase is stopped on this
16 idle states and so on. The flag bits are as follows:
18 - exit-latency: The latency involved in transitioning the state of the
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| /Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,idle-state.txt | 1 QCOM Idle States for cpuidle driver
3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
5 states. Idle states have different enter/exit latency and residency values.
6 The idle states supported by the QCOM SoC are defined as -
18 hierarchy to enter standby states, when all cpus are idle. An interrupt brings
20 cache hierarchy is also out of standby, and then the cpu is allowed to resume
30 sequence and would wait for interrupt, before restoring the cpu to execution
33 Standalone PC: A cpu can power down and warmboot if there is a sufficient time
34 between the time it enters idle and the next known wake up. SPC mode is used
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| /Documentation/admin-guide/pm/ |
| D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 .. |cpufreq| replace:: :doc:`CPU Performance Scaling <cpufreq>`
8 CPU Idle Time Management
19 Modern processors are generally able to enter states in which the execution of
21 memory or executed. Those states are the *idle* states of the processor.
23 Since part of the processor hardware is not used in idle states, entering them
27 CPU idle time management is an energy-efficiency feature concerned about using
28 the idle states of processors for this purpose.
31 ------------
33 CPU idle time management operates on CPUs as seen by the *CPU scheduler* (that
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| D | sleep-states.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 System Sleep States
13 Sleep states are global low-power states of the entire system in which user
18 Sleep States That Can Be Supported
22 the Linux kernel can support up to four system sleep states, including
23 hibernation and up to three variants of system suspend. The sleep states that
28 Suspend-to-Idle
29 ---------------
31 This is a generic, pure software, light-weight variant of system suspend (also
33 runtime idle by freezing user space, suspending the timekeeping and putting all
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| D | cpufreq.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 CPU Performance Scaling
16 The Concept of CPU Performance Scaling
21 Operating Performance Points or P-states (in ACPI terminology). As a rule,
23 can be retired by the CPU over a unit of time, but also the higher the clock
25 time (or the more power is drawn) by the CPU in the given P-state. Therefore
26 there is a natural tradeoff between the CPU capacity (the number of instructions
27 that can be executed over a unit of time) and the power drawn by the CPU.
30 as possible and then there is no reason to use any P-states different from the
31 highest one (i.e. the highest-performance frequency/voltage configuration
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| /Documentation/driver-api/pm/ |
| D | cpuidle.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 CPU Idle Time Management
18 CPU Idle Time Management Subsystem
23 cores) is idle after an interrupt or equivalent wakeup event, which means that
24 there are no tasks to run on it except for the special "idle" task associated
26 belongs to. That can be done by making the idle logical CPU stop fetching
28 depended on by it into an idle state in which they will draw less power.
30 However, there may be multiple different idle states that can be used in such a
33 particular idle state. That is the role of the CPU idle time management
40 units: *governors* responsible for selecting idle states to ask the processor
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| /Documentation/driver-api/thermal/ |
| D | intel_powerclamp.rst | 6 - Arjan van de Ven <arjan@linux.intel.com>
7 - Jacob Pan <jacob.jun.pan@linux.intel.com>
12 - Goals and Objectives
15 - Idle Injection
16 - Calibration
19 - Effectiveness and Limitations
20 - Power vs Performance
21 - Scalability
22 - Calibration
23 - Comparison with Alternative Techniques
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| /Documentation/firmware-guide/acpi/ |
| D | lpit.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Low Power Idle Table (LPIT)
7 To enumerate platform Low Power Idle states, Intel platforms are using
8 “Low Power Idle Table” (LPIT). More details about this table can be
15 On platforms supporting S0ix sleep states, there can be two types of
18 - CPU PKG C10 (Read via FFH interface)
19 - Platform Controller Hub (PCH) SLP_S0 (Read via memory mapped interface)
24 /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
25 /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us
28 by the CPU package in PKG C10
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| /Documentation/trace/ |
| D | coresight-cpu-debug.rst | 2 Coresight CPU Debug Module
9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
20 to sample CPU program counter, secure state and exception level, etc; usually
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
24 will dump related registers for every CPU; finally this is good for assistant
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| D | events-power.rst | 8 - Power state switch which reports events related to suspend (S-states),
9 cpuidle (C-states) and cpufreq (P-states)
10 - System clock related changes
11 - Power domains related changes and transitions
22 -----------------
24 A 'cpu' event class gathers the CPU-related events: cpuidle and
39 Note: the value of '-1' or '4294967295' for state means an exit from the current state,
41 enters the idle state 4, while trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id())
42 means that the system exits the previous idle state.
46 correctly draw the states diagrams and to calculate accurate statistics etc.
|
| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-mediatek.txt | 5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
9 source (usually MAINPLL) when the original CPU PLL is under
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - #cooling-cells:
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| /Documentation/RCU/Design/Memory-Ordering/ |
| D | Tree-RCU-Memory-Ordering.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"
4 <head><title>A Tour Through TREE_RCU's Grace-Period Memory Ordering</title>
5 <meta HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
13 grace-period memory ordering guarantee is provided.
28 <p>RCU grace periods provide extremely strong memory-ordering guarantees
29 for non-idle non-offline code.
32 period that are within RCU read-side critical sections.
35 of that grace period that are within RCU read-side critical sections.
37 <p>Note well that RCU-sched read-side critical sections include any region
40 an extremely small region of preemption-disabled code, one can think of
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| /Documentation/RCU/ |
| D | stallwarn.txt | 1 Using RCU's CPU Stall Detector
3 This document first discusses what sorts of issues RCU's CPU stall
5 options that can be used to fine-tune the detector's operation. Finally,
9 What Causes RCU CPU Stall Warnings?
11 So your kernel printed an RCU CPU stall warning. The next question is
12 "What caused it?" The following problems can result in RCU CPU stall
15 o A CPU looping in an RCU read-side critical section.
17 o A CPU looping with interrupts disabled.
19 o A CPU looping with preemption disabled.
21 o A CPU looping with bottom halves disabled.
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| D | rcu.rst | 6 The basic idea behind RCU (read-copy update) is to split destructive
11 since dropped their references. For example, an RCU-protected deletion
18 --------------------------
20 - Why would anyone want to use RCU?
22 The advantage of RCU's two-part approach is that RCU readers need
27 in read-mostly situations. The fact that RCU readers need not
28 acquire locks can also greatly simplify deadlock-avoidance code.
30 - How can the updater tell when a grace period has completed
34 block, switch to user-mode execution, or enter the idle loop.
35 Therefore, as soon as a CPU is seen passing through any of these
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| /Documentation/ABI/testing/ |
| D | sysfs-devices-system-cpu | 1 What: /sys/devices/system/cpu/
2 Date: pre-git history
3 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
5 A collection of both global and individual CPU attributes
7 Individual CPU attributes are contained in subdirectories
8 named by the kernel's logical CPU number, e.g.:
10 /sys/devices/system/cpu/cpu#/
12 What: /sys/devices/system/cpu/kernel_max
13 /sys/devices/system/cpu/offline
14 /sys/devices/system/cpu/online
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| /Documentation/RCU/Design/Expedited-Grace-Periods/ |
| D | Expedited-Grace-Periods.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"
5 <meta HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
15 There are two flavors of RCU (RCU-preempt and RCU-sched), with an earlier
16 third RCU-bh flavor having been implemented in terms of the other two.
22 <li> <a href="#RCU-preempt Expedited Grace Periods">
23 RCU-preempt Expedited Grace Periods</a>
24 <li> <a href="#RCU-sched Expedited Grace Periods">
25 RCU-sched Expedited Grace Periods</a>
26 <li> <a href="#Expedited Grace Period and CPU Hotplug">
27 Expedited Grace Period and CPU Hotplug</a>
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| /Documentation/RCU/Design/Data-Structures/ |
| D | Data-Structures.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"
5 <meta HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
16 <li> <a href="#Data-Structure Relationships">
17 Data-Structure Relationships</a>
28 <li> <a href="#RCU-Specific Fields in the task_struct Structure">
29 RCU-Specific Fields in the <tt>task_struct</tt> Structure</a>
34 <h3><a name="Data-Structure Relationships">Data-Structure Relationships</a></h3>
50 one for each possible CPU.
55 which results in a three-level <tt>rcu_node</tt> tree.
59 </p><p>The purpose of this combining tree is to allow per-CPU events
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| /Documentation/devicetree/bindings/mmc/ |
| D | ti-omap-hsmmc.txt | 10 --------------------
11 - compatible:
12 Should be "ti,omap2-hsmmc", for OMAP2 controllers
13 Should be "ti,omap3-hsmmc", for OMAP3 controllers
14 Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
15 Should be "ti,omap4-hsmmc", for OMAP4 controllers
16 Should be "ti,am33xx-hsmmc", for AM335x controllers
17 Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers.
20 ---------------------------------
22 - ti,hwmods: Must be "mmc<n>", n is controller instance starting 1.
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| /Documentation/admin-guide/ |
| D | cpu-load.rst | 2 CPU load
10 Linux 2.6.18.3-exp (linmac) 02/20/2007
12 avg-cpu: %user %nice %system %iowait %steal %idle
19 kernel, and was overall 81.63% of the time idle.
29 switched between various states multiple times between two timer
34 -------
40 |--------------------------------------|
48 system is executing the idle handler), but in reality the load is
55 /* gcc -o hog smallhog.c */
72 while (!stop && --niters);
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| /Documentation/arm/ |
| D | cluster-pm-race-avoidance.rst | 2 Cluster-wide Power-up/power-down race avoidance algorithm
5 This file documents the algorithm which is used to coordinate CPU and
16 ---------
19 ability to turn off individual CPUs when the system is idle, reducing
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
48 Each cluster and CPU is assigned a state, as follows:
50 - DOWN
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| /Documentation/core-api/ |
| D | cpu_hotplug.rst | 2 CPU hotplug in the Kernel
18 insertion and removal require support for CPU hotplug.
21 provisioning reasons, or for RAS purposes to keep an offending CPU off
22 system execution path. Hence the need for CPU hotplug support in the
25 A more novel use of CPU-hotplug support is its use today in suspend resume
26 support for SMP. Dual-core and HT support makes even a laptop run SMP kernels
65 CPU maps
78 after a CPU is available for kernel scheduling and ready to receive
79 interrupts from devices. Its cleared when a CPU is brought down using
81 migrated to another target CPU.
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