Home
last modified time | relevance | path

Searched +full:cpu +full:- +full:intc (Results 1 – 25 of 30) sorted by relevance

12

/Documentation/devicetree/bindings/mips/
Dcpu_irq.txt1 MIPS CPU interrupt controller
3 On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
13 - compatible : Should be "mti,cpu-interrupt-controller"
16 cpu-irq: cpu-irq {
17 #address-cells = <0>;
19 interrupt-controller;
20 #interrupt-cells = <1>;
22 compatible = "mti,cpu-interrupt-controller";
25 intc: intc@200 {
26 compatible = "ralink,rt2880-intc";
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dqca,ath79-cpu-intc.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
9 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
13 source, should be 1 for intc
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
28 interrupt-controller {
[all …]
Dqca,ath79-misc-intc.txt7 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
8 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
9 - reg: Base address and size of the controllers memory area
10 - interrupts: Interrupt specifier for the controllers interrupt.
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
23 interrupt-controller@18060010 {
24 compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
27 interrupt-parent = <&cpuintc>;
30 interrupt-controller;
[all …]
Dbrcm,bcm6345-l1-intc.txt1 Broadcom BCM6345-style Level 1 interrupt controller
4 directly to one of the HW INT lines on each CPU.
8 - 32, 64 or 128 incoming level IRQ lines
10 - Most onchip peripherals are wired directly to an L1 input
12 - A separate instance of the register set for each CPU, allowing individual
13 peripheral IRQs to be routed to any CPU
15 - Contains one or more enable/status word pairs per CPU
17 - No atomic set/clear operations
19 - No polarity/level/edge settings
21 - No FIFO or priority encoder logic; software is expected to read all
[all …]
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
28 - #interrupt-cells : should be <1>. The interrupt sources are defined by the
[all …]
Dingenic,intc.txt5 - compatible : should be "ingenic,<socname>-intc". Valid strings are:
6 ingenic,jz4740-intc
7 ingenic,jz4725b-intc
8 ingenic,jz4770-intc
9 ingenic,jz4775-intc
10 ingenic,jz4780-intc
11 - reg : Specifies base physical address and size of the registers.
12 - interrupt-controller : Identifies the node as an interrupt controller
13 - #interrupt-cells : Specifies the number of cells needed to encode an
15 - interrupts : Specifies the CPU interrupt the controller is connected to.
[all …]
Dcsky,apb-intc.txt2 C-SKY APB Interrupt Controller
5 C-SKY APB Interrupt Controller is a simple soc interrupt controller
8 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
9 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
10 - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
13 intc node bindings definition
20 - compatible
23 Definition: must be "csky,apb-intc"
24 "csky,dual-apb-intc"
25 "csky,gx6605s-intc"
[all …]
Dloongson,ls1x-intc.txt5 - compatible : should be "loongson,ls1x-intc". Valid strings are:
7 - reg : Specifies base physical address and size of the registers.
8 - interrupt-controller : Identifies the node as an interrupt controller
9 - #interrupt-cells : Specifies the number of cells needed to encode an
11 - interrupts : Specifies the CPU interrupt the controller is connected to.
15 intc: interrupt-controller@1fd01040 {
16 compatible = "loongson,ls1x-intc";
19 interrupt-controller;
20 #interrupt-cells = <2>;
22 interrupt-parent = <&cpu_intc>;
Dbrcm,bcm2836-l1-intc.txt1 BCM2836 per-CPU interrupt controller
3 The BCM2836 has a per-cpu interrupt controller for the timer, PMU
5 peripheral (GPU) events, which chain to the BCM2835-style interrupt
10 - compatible: Should be "brcm,bcm2836-l1-intc"
11 - reg: Specifies base physical address and size of the
13 - interrupt-controller: Identifies the node as an interrupt controller
14 - #interrupt-cells: Specifies the number of cells needed to encode an
32 compatible = "brcm,bcm2836-l1-intc";
34 interrupt-controller;
35 #interrupt-cells = <2>;
[all …]
Dsifive,plic-1.0.0.txt1 SiFive Platform-Level Interrupt Controller (PLIC)
2 -------------------------------------------------
4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
5 (PLIC) high-level specification in the RISC-V Privileged Architecture
10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
13 Each interrupt can be enabled on per-context basis. Any context can claim
21 While the PLIC supports both edge-triggered and level-triggered interrupts,
23 specified in the PLIC device-tree binding.
25 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
26 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
[all …]
Dbrcm,bcm7038-l1-intc.txt1 Broadcom BCM7038-style Level 1 interrupt controller
4 directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
9 - 64, 96, 128, or 160 incoming level IRQ lines
11 - Most onchip peripherals are wired directly to an L1 input
13 - A separate instance of the register set for each CPU, allowing individual
14 peripheral IRQs to be routed to any CPU
16 - Atomic mask/unmask operations
18 - No polarity/level/edge settings
20 - No FIFO or priority encoder logic; software is expected to read all
21 2-5 status words to determine which IRQs are pending
[all …]
Dabilis,tb10x-ictl.txt5 one-to-one mapping of external interrupt sources to CPU interrupts and
9 -------------------
11 - compatible: Should be "abilis,tb10x-ictl"
12 - reg: specifies physical base address and size of register range.
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
16 - interrupts: Specifies the list of interrupt lines which are handled by
18 are mapped one-to-one to parent interrupts.
21 -------
23 intc: interrupt-controller { /* Parent interrupt controller */
[all …]
Dmscc,ocelot-icpu-intr.txt5 - compatible : should be "mscc,ocelot-icpu-intr"
6 - reg : Specifies base physical address and size of the registers.
7 - interrupt-controller : Identifies the node as an interrupt controller
8 - #interrupt-cells : Specifies the number of cells needed to encode an
10 - interrupts : Specifies the CPU interrupt the controller is connected to.
14 intc: interrupt-controller@70000070 {
15 compatible = "mscc,ocelot-icpu-intr";
17 #interrupt-cells = <1>;
18 interrupt-controller;
19 interrupt-parent = <&cpuintc>;
Dbrcm,bcm2835-armctrl-ic.txt1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
9 interrupts, but the per-CPU interrupt controller is the root, and an
14 - compatible : should be "brcm,bcm2835-armctrl-ic" or
15 "brcm,bcm2836-armctrl-ic"
16 - reg : Specifies base physical address and size of the registers.
17 - interrupt-controller : Identifies the node as an interrupt controller
18 - #interrupt-cells : Specifies the number of cells needed to encode an
28 Additional required properties for brcm,bcm2836-armctrl-ic:
[all …]
Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
[all …]
/Documentation/devicetree/bindings/cpufreq/
Dbrcm,stb-avs-cpu-freq.txt4 A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
5 references the mailbox register used to communicate with the AVS CPU[1]. The
6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
7 the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
8 command sent to it by a driver. Interrupting the AVS CPU is mandatory for
12 so a driver can react to interrupts generated by the AVS CPU whenever a command
13 has been processed. See [2] for more information on the brcm,l2-intc node.
15 [1] The AVS CPU is an independent co-processor that runs proprietary
19 [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
22 Node brcm,avs-cpu-data-mem
[all …]
/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
[all …]
/Documentation/devicetree/bindings/arm/ux500/
Dboards.txt1 ST-Ericsson Ux500 boards
2 ------------------------
5 compatible = "st-ericsson,mop500" (legacy)
6 compatible = "st-ericsson,u8500"
10 soc: represents the system-on-chip and contains the chip
18 backupram: (used for CPU spin tables and for storing data
20 compatible = "ste,dbx500-backupram"
25 interrupt-controller:
26 see binding for interrupt-controller/arm,gic.txt
36 /dts-v1/;
[all …]
/Documentation/devicetree/bindings/arm/freescale/
Dfsl,vf610-mscm-ir.txt1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
8 which comes with a Cortex-A5/Cortex-M4 combination).
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
14 to get the current CPU ID
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
23 mscm_ir: interrupt-controller@40001800 {
24 compatible = "fsl,vf610-mscm-ir";
[all …]
/Documentation/devicetree/bindings/timer/
Dcsky,gx6605s-timer.txt16 - compatible
19 Definition: must be "csky,gx6605s-timer"
20 - reg
23 Definition: <phyaddr size> in soc from cpu view
24 - clocks
28 - interrupt
34 ---------
37 compatible = "csky,gx6605s-timer";
41 interrupt-parent = <&intc>;
Dcsky,mptimer.txt2 C-SKY Multi-processors Timer
5 C-SKY multi-processors timer is designed for C-SKY SMP system and the
6 regs is accessed by cpu co-processor 4 registers with mtcr/mfcr.
8 - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer.
9 - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg.
10 - PTIM_CCVR "cr<3, 14>" Current counter value reg.
11 - PTIM_LVR "cr<6, 14>" Window value reg to triger next event.
21 - compatible
25 - clocks
29 - interrupts
[all …]
/Documentation/devicetree/bindings/csky/
Dpmu.txt2 C-SKY Performance Monitor Units
5 C-SKY Performance Monitor is designed for ck807/ck810/ck860 SMP soc and
6 it could count cpu's events for helping analysis performance issues.
16 - compatible
19 Definition: must be "csky,csky-pmu"
20 - interrupts
24 - count-width
30 ---------
31 #include <dt-bindings/interrupt-controller/irq.h>
33 pmu: performace-monitor {
[all …]
/Documentation/x86/i386/
DIO-APIC.rst1 .. SPDX-License-Identifier: GPL-2.0
4 IO-APIC
9 Most (all) Intel-MP compliant SMP boards have the so-called 'IO-APIC',
11 hardware interrupts to multiple CPUs, or to CPU groups. Without an
12 IO-APIC, interrupts from hardware will be delivered only to the
13 CPU which boots the operating system (usually CPU#0).
16 multiple IO-APICs. Multiple IO-APICs are used in high-end servers to
20 usually worked around by the kernel. If your MP-compliant SMP board does
21 not boot Linux, then consult the linux-smp mailing list archives first.
23 If your box boots fine with enabled IO-APIC IRQs, then your
[all …]
/Documentation/devicetree/bindings/remoteproc/
Dti,davinci-rproc.txt4 Binding status: Unstable - Subject to changes for DT representation of clocks
7 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
8 is used to offload some of the processor-intensive tasks or algorithms, for
11 The processor cores in the sub-system usually contain additional sub-modules
14 core used in Davinci SoCs is usually a C674x DSP CPU.
18 Each DSP Core sub-system is represented as a single DT node.
21 --------------------
24 - compatible: Should be one of the following,
25 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
27 - reg: Should contain an entry for each value in 'reg-names'.
[all …]
/Documentation/devicetree/bindings/mmc/
Dti-omap-hsmmc.txt10 --------------------
11 - compatible:
12 Should be "ti,omap2-hsmmc", for OMAP2 controllers
13 Should be "ti,omap3-hsmmc", for OMAP3 controllers
14 Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
15 Should be "ti,omap4-hsmmc", for OMAP4 controllers
16 Should be "ti,am33xx-hsmmc", for AM335x controllers
17 Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers.
20 ---------------------------------
22 - ti,hwmods: Must be "mmc<n>", n is controller instance starting 1.
[all …]

12