Searched +full:cpu +full:- +full:offset (Results 1 – 25 of 140) sorted by relevance
123456
| /Documentation/devicetree/bindings/timer/ |
| D | qcom,msm-timer.txt | 5 - compatible : Should at least contain "qcom,msm-timer". More specific
8 "qcom,kpss-timer" - krait subsystem
9 "qcom,scss-timer" - scorpion subsystem
11 - interrupts : Interrupts for the debug timer, the first general purpose
15 - reg : Specifies the base address of the timer registers.
17 - clocks: Reference to the parent clocks, one per output clock. The parents
20 - clock-names: The name of the clocks as free-form strings. They should be in
23 - clock-frequency : The frequency of the debug timer and the general purpose
28 - cpu-offset : per-cpu offset used when the timer is accessed without the
29 CPU remapping facilities. The offset is
[all …]
|
| /Documentation/ |
| D | this_cpu_ops.txt | 8 this_cpu operations are a way of optimizing access to per cpu
11 the cpu permanently stored the beginning of the per cpu area for a
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
19 the offset and the operation on the data. Therefore it is not
24 Read-modify-write operations are of particular interest. Frequently
32 synchronization is not necessary since we are dealing with per cpu
37 Please note that accesses by remote processors to a per cpu area are
66 ------------------------------------
[all …]
|
| D | io-mapping.txt | 8 The io_mapping functions in linux/io-mapping.h provide an abstraction for
9 efficiently mapping small regions of an I/O device to the CPU. The initial
10 usage is to support the large graphics aperture on 32-bit processors where
11 ioremap_wc cannot be used to statically map the entire aperture to the CPU
31 unsigned long offset)
33 'offset' is the offset within the defined mapping region.
35 creation function yields undefined results. Using an offset
37 return value points to a single page in CPU address space.
39 This _wc variant returns a write-combining map to the
54 If you need to sleep while holding the lock, you can use the non-atomic
[all …]
|
| /Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,bcm63138.txt | 1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
11 An optional Boot lookup table Device Tree node is required for secondary CPU
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
20 Optional properties for the primary CPU node:
21 - enable-method: should be "brcm,bcm63138"
[all …]
|
| D | brcm,brcmstb.txt | 2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
23 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
[all …]
|
| /Documentation/scsi/ |
| D | hptiop.txt | 4 -------------------------
8 BAR0 offset Register
12 BAR2 offset Register
27 BAR0 offset Register
42 BAR0 offset Register
48 BAR1 offset Register
55 0x40-0x1040 Inbound Queue
56 0x1040-0x2040 Outbound Queue
60 BAR0 offset Register
63 BAR1 offset Register
[all …]
|
| /Documentation/devicetree/bindings/arm/cpu-enable-method/ |
| D | al,alpine-smp | 2 Secondary CPU enable-method "al,alpine-smp" binding
5 This document describes the "al,alpine-smp" method for
7 "al,alpine-smp" enable method should be defined in the
10 Enable method name: "al,alpine-smp"
12 Compatible CPUs: "arm,cortex-a15"
17 "al,alpine-cpu-resume" and "al,alpine-nb-service".
20 * Alpine CPU resume registers
22 The CPU resume register are used to define required resume address after
26 - compatible : Should contain "al,alpine-cpu-resume".
27 - reg : Offset and length of the register set for the device
[all …]
|
| /Documentation/virt/kvm/devices/ |
| D | arm-vgic.txt | 9 controller, requiring emulated user-space devices to inject interrupts to the
14 device and guest ITS devices, see arm-vgic-v3.txt. It is not possible to
21 KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit)
26 KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit)
27 Base address in the guest physical address space of the GIC virtual cpu
31 -E2BIG: Address outside of addressable IPA range
32 -EINVAL: Incorrectly aligned address
33 -EEXIST: Address already configured
34 -ENXIO: The group or attribute is unknown/unsupported for this device
36 -EFAULT: Invalid user pointer for attr->addr.
[all …]
|
| /Documentation/trace/ |
| D | coresight-cpu-debug.rst | 2 Coresight CPU Debug Module
9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
20 to sample CPU program counter, secure state and exception level, etc; usually
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
24 will dump related registers for every CPU; finally this is good for assistant
[all …]
|
| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dcsr.txt | 21 - compatible
24 Definition: Must include "fsl,dcsr" and "simple-bus".
25 The DCSR space exists in the memory-mapped bus.
27 - #address-cells
33 - #size-cells
40 - ranges
42 Value type: <prop-encoded-array>
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "fsl,dcsr", "simple-bus";
[all …]
|
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
[all …]
|
| /Documentation/arm/samsung/ |
| D | bootloader-interface.rst | 14 In the document "boot loader" means any of following: U-boot, proprietary
19 1. Non-Secure mode
24 Offset Value Purpose
28 0x1c exynos4_secondary_startup Secondary CPU boot
29 0x1c + 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
32 0x28 + 4*cpu 0x8 (Magic cookie, Exynos3250) AFTR
42 Offset Value Purpose
44 0x00 exynos4_secondary_startup Secondary CPU boot
45 0x04 exynos4_secondary_startup (Exynos542x) Secondary CPU boot
46 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
[all …]
|
| /Documentation/devicetree/bindings/arm/hisilicon/ |
| D | hisilicon.txt | 2 ----------------------------------------------------
5 - compatible = "hisilicon,hi3660";
9 - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
13 - compatible = "hisilicon,hi3670";
17 - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
21 - compatible = "hisilicon,hi3798cv200";
25 - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
29 - compatible = "hisilicon,hi3620-hi4511";
33 - compatible = "hisilicon,hi6220";
37 - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
[all …]
|
| /Documentation/ABI/testing/ |
| D | sysfs-bus-event_source-devices-events | 1 What: /sys/devices/cpu/events/
2 /sys/devices/cpu/events/branch-misses
3 /sys/devices/cpu/events/cache-references
4 /sys/devices/cpu/events/cache-misses
5 /sys/devices/cpu/events/stalled-cycles-frontend
6 /sys/devices/cpu/events/branch-instructions
7 /sys/devices/cpu/events/stalled-cycles-backend
8 /sys/devices/cpu/events/instructions
9 /sys/devices/cpu/events/cpu-cycles
13 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
[all …]
|
| /Documentation/devicetree/bindings/opp/ |
| D | ti-omap5-opp-supply.txt | 9 Also, some supplies may have an associated vbb-supply which is an Adaptive Body
11 to the vdd-supply and clk when making an OPP transition. By supplying two
19 - vdd-supply: phandle to regulator controlling VDD supply
20 - vbb-supply: phandle to regulator controlling Body Bias supply
23 Required Properties for opp-supply node:
24 - compatible: Should be one of:
25 "ti,omap-opp-supply" - basic OPP supply controlling VDD and VBB
26 "ti,omap5-opp-supply" - OMAP5+ optimized voltages in efuse(class0)VDD
28 "ti,omap5-core-opp-supply" - OMAP5+ optimized voltages in efuse(class0) VDD
30 - reg: Address and length of the efuse register set for the device (mandatory
[all …]
|
| /Documentation/devicetree/bindings/spi/ |
| D | fsl-spi.txt | 4 - cell-index : QE SPI subblock index.
7 - compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
8 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
9 - reg : Offset and length of the register set for the device
10 - interrupts : <a b> where a is the interrupt number and b is a
15 - clock-frequency : input clock frequency to non FSL_SOC cores
18 - gpios : specifies the gpio pins to be used for chipselects.
21 - fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the
28 cell-index = <0>;
32 interrupt-parent = <700>;
[all …]
|
| /Documentation/devicetree/bindings/arm/marvell/ |
| D | ap806-system-controller.txt | 6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP806 system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
[all …]
|
| /Documentation/hwmon/ |
| D | smsc47m192.rst | 10 Addresses scanned: I2C 0x2c - 0x2d
23 - Hartmut Rick <linux@rick.claranet.de>
25 - Special thanks to Jean Delvare for careful checking
30 -----------
33 of the SMSC LPC47M192 and compatible Super-I/O chips.
36 as well as CPU voltage VID input.
42 Voltages and temperatures are measured by an 8-bit ADC, the resolution
52 bit 4 of the encoded CPU voltage. This means that you either get
53 a +12V voltage measurement or a 5 bit CPU VID, but not both.
64 ---------------
[all …]
|
| /Documentation/arm64/ |
| D | booting.rst | 13 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
14 counterpart. EL2 is the hypervisor level and exists only in non-secure
18 simply to define all software that executes on the CPU(s) before control
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
79 u64 text_offset; /* Image load offset, little endian */
[all …]
|
| /Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,saw2.txt | 5 power-controller that transitions a piece of hardware (like a processor or
11 SAW2 revisions differ in the register offset and configuration data. Also, the
14 version of the SAW hardware in that SoC and the distinction between cpu (big
21 - compatible:
27 "qcom,apq8064-saw2-v1.1-cpu"
28 "qcom,msm8974-saw2-v2.1-cpu"
29 "qcom,apq8084-saw2-v2.1-cpu"
31 - reg:
33 Value type: <prop-encoded-array>
38 - regulator:
[all …]
|
| /Documentation/devicetree/bindings/powerpc/4xx/ |
| D | cpm.txt | 4 - compatible : compatible list, currently only "ibm,cpm"
5 - dcr-access-method : "native"
6 - dcr-reg : < DCR register range >
9 - er-offset : All 4xx SoCs with a CPM controller have
15 er-offset = <1>.
16 - unused-units : specifier consist of one cell. For each
20 - idle-doze : specifier consist of one cell. For each
23 devices. This is usually just CPM[CPU].
24 - standby : specifier consist of one cell. For each
28 - suspend : specifier consist of one cell. For each
[all …]
|
| /Documentation/devicetree/bindings/bus/ |
| D | uniphier-system-bus.txt | 3 The UniPhier System Bus is an external bus that connects on-board devices to
4 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
8 controller registers provide the control for the translation from the offset
9 within each bank to the CPU-viewed address. The needed setup includes the base
14 - compatible: should be "socionext,uniphier-system-bus".
15 - reg: offset and length of the register set for the bus controller device.
16 - #address-cells: should be 2. The first cell is the bank number (chip select).
17 The second cell is the address offset within the bank.
18 - #size-cells: should be 1.
19 - ranges: should provide a proper address translation from the System Bus to
[all …]
|
| /Documentation/core-api/ |
| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
13 due to potential endianness mismatches between the CPU and the hardware device.
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
37 into a CPU-usable number.
[all …]
|
| /Documentation/devicetree/bindings/display/ |
| D | zte,vou.txt | 10 It must be the parent node of all the sub-device nodes.
13 - compatible: should be "zte,zx296718-vou"
14 - #address-cells: should be <1>
15 - #size-cells: should be <1>
16 - ranges: list of address translations between VOU and sub-devices
21 - compatible: should be "zte,zx296718-dpc"
22 - reg: Physical base address and length of DPC register regions, one for each
23 entry in 'reg-names'
24 - reg-names: The names of register regions. The following regions are required:
30 - interrupts: VOU DPC interrupt number to CPU
[all …]
|
| /Documentation/vm/ |
| D | page_frags.rst | 7 A page fragment is an arbitrary-length arbitrary-offset area of memory
15 memory for use as either an sk_buff->head, or to be used in the "frags"
24 either a per-cpu limitation, or a per-cpu limitation and forcing interrupts
27 The network stack uses two separate caches per CPU to handle fragment
|
123456