Searched +full:cpu +full:- +full:registers +full:- +full:not +full:- +full:fw +full:- +full:configured (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Marc Zyngier <marc.zyngier@arm.com>11 - Mark Rutland <mark.rutland@arm.com>13 ARM cores may have a per-core architected timer, which provides per-cpu timers,17 The per-core architected timer is attached to a GIC to deliver its18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC24 - items:25 - enum:[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Marc Zyngier <marc.zyngier@arm.com>11 - Mark Rutland <mark.rutland@arm.com>22 - enum:23 - arm,armv7-timer-mem29 '#address-cells':32 '#size-cells':35 clock-frequency:[all …]
35 that's not critical.57 - For DMA we then provide an entire address space for each PE that can59 Each window can be configured to be remapped via a "TCE table" (IOMMU61 not described here.63 - For MSIs, we have two windows in the address space (one at the top of64 the 32-bit space and one much higher) which, via a combination of the70 - Error messages just use the RTT.75 from the CPU address space to the PCI address space. There is one M3278 the CPU address space to the PCIe bus and must be naturally aligned81 - The M32 window:[all …]